Commit 48f2b923 authored by whitequark's avatar whitequark
Browse files

doc/fhdl: use correct syntax for code block.

parent e66f2df8
...@@ -359,7 +359,7 @@ The clock domain management mechanism explained above happens during finalizatio ...@@ -359,7 +359,7 @@ The clock domain management mechanism explained above happens during finalizatio
Conversion for synthesis Conversion for synthesis
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Any FHDL module can be converted into synthesizable Verilog HDL. This is accomplished by using the ``convert`` function in the ``migen.fhdl.verilog`` module: Any FHDL module can be converted into synthesizable Verilog HDL. This is accomplished by using the ``convert`` function in the ``migen.fhdl.verilog`` module: ::
# define FHDL module MyDesign here # define FHDL module MyDesign here
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