- 09 Oct, 2018 1 commit
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whitequark authored
str(value) serializes to e.g. <Constant object at 0x7f3f94f346d8>, which is randomized due to ASLR even with e.g. PYTHONHASHSEED set.
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- 04 Oct, 2018 2 commits
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N. Engelhardt authored
add a print to show user context when an exception is raised while evaluating a generator yield statement in simulation
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William D. Jones authored
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- 02 Oct, 2018 1 commit
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Piotr Esden-Tempski authored
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- 21 Sep, 2018 1 commit
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Piotr Esden-Tempski authored
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- 20 Sep, 2018 1 commit
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hartytp authored
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- 19 Sep, 2018 2 commits
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Sebastien Bourdeauducq authored
Breaks inouts with vivado. This reverts commit 2a7e33e9.
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hartytp authored
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- 17 Sep, 2018 2 commits
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whitequark authored
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whitequark authored
When filing a bug report, it is useful to have the complete toolchain invocation, including synthesis and P&R command line options.
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- 10 Sep, 2018 1 commit
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David Craven authored
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- 04 Sep, 2018 1 commit
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William D. Jones authored
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- 29 Aug, 2018 1 commit
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Robert Jördens authored
* Set USR_ACCESS to a timestamp. that enables a bit of bitstream forensics when the origin is unclear. * Set USERID to all-ones. E.g. misoc/artiq can set it to a shortened git hash.
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- 28 Aug, 2018 1 commit
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William D. Jones authored
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- 21 Aug, 2018 1 commit
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Daniel Kucera authored
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- 17 Aug, 2018 1 commit
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Robin Ole Heinemann authored
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- 13 Aug, 2018 1 commit
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William D. Jones authored
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- 30 Jul, 2018 4 commits
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whitequark authored
Only useful in simulation to avoid junk transitions and their effect without (slowly) simulating power-on-reset logic.
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whitequark authored
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whitequark authored
Tristate support in Yosys is "experimental", as it warns every time it encounters a tristate assign, and indeed there is a number of bugs that can be hit if doing anything non-trivial with Yosys and Arachne.
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whitequark authored
Before this commit, convert() mutated the input fragment, and calling it twice on the same fragment produced invalid Verilog because e.g. specials get lowered twice.
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- 29 Jul, 2018 1 commit
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whitequark authored
This is similar to what misoc's CSR registers provide.
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- 26 Jul, 2018 1 commit
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Sebastien Bourdeauducq authored
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- 24 Jul, 2018 2 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 17 Jul, 2018 3 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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William D. Jones authored
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- 11 Jul, 2018 1 commit
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Sebastien Bourdeauducq authored
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- 05 Jul, 2018 1 commit
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Florent Kermarrec authored
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- 03 Jul, 2018 1 commit
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Thomas Harty authored
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- 27 Jun, 2018 1 commit
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Sebastien Bourdeauducq authored
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- 25 Jun, 2018 2 commits
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Sebastien Bourdeauducq authored
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Sebastien Bourdeauducq authored
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- 23 Jun, 2018 1 commit
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whitequark authored
Fixes #114.
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- 22 Jun, 2018 5 commits
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Caleb Jamison authored
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Caleb Jamison authored
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Caleb Jamison authored
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Caleb Jamison authored
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Caleb Jamison authored
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