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Kestrel Collaboration
Kestrel LiteX
migen
Commits
18274c3c
Commit
18274c3c
authored
6 years ago
by
whitequark
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build.lattice: fix IcestormTristate override for 1-bit signals.
parent
e07c1c5d
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1
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16 additions
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4 deletions
+16
-4
migen/build/lattice/common.py
migen/build/lattice/common.py
+16
-4
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migen/build/lattice/common.py
View file @
18274c3c
from
migen.fhdl.module
import
Module
from
migen.fhdl.specials
import
Instance
,
Tristate
from
migen.fhdl.bitcontainer
import
value_bits_sign
from
migen.genlib.io
import
*
from
migen.genlib.resetsync
import
AsyncResetSynchronizer
...
...
@@ -59,15 +60,26 @@ class IcestormAsyncResetSynchronizer:
class
IcestormTristateImpl
(
Module
):
def
__init__
(
self
,
io
,
o
,
oe
,
i
):
for
bit
in
range
(
io
.
nbits
):
nbits
,
sign
=
value_bits_sign
(
io
)
if
nbits
==
1
:
self
.
specials
+=
\
Instance
(
"SB_IO"
,
p_PIN_TYPE
=
C
(
0b101001
,
6
),
io_PACKAGE_PIN
=
io
[
bit
]
,
io_PACKAGE_PIN
=
io
,
i_OUTPUT_ENABLE
=
oe
,
i_D_OUT_0
=
o
[
bit
]
,
o_D_IN_0
=
i
[
bit
]
,
i_D_OUT_0
=
o
,
o_D_IN_0
=
i
,
)
else
:
for
bit
in
range
(
nbits
):
self
.
specials
+=
\
Instance
(
"SB_IO"
,
p_PIN_TYPE
=
C
(
0b101001
,
6
),
io_PACKAGE_PIN
=
io
[
bit
],
i_OUTPUT_ENABLE
=
oe
,
i_D_OUT_0
=
o
[
bit
],
o_D_IN_0
=
i
[
bit
],
)
class
IcestormTristate
(
Module
):
...
...
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