- 12 Mar, 2021 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 04 Mar, 2021 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
frontend/dma: Modify CSR interface to be similar to LiteX's DMA (start becomes a enable), also add offset CSR to keep track of current status.
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- 03 Mar, 2021 2 commits
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Florent Kermarrec authored
frontend/dma: Add default CSR values to add_csr. (Allow initializing DMA after reset without software intervention).
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Florent Kermarrec authored
The fabric is now maintaining an increment counter for each DQS's ODELAY and software use it to revert total increments to 0 (equivalent to a reset). Avoiding the separate ODELAYE3 simplifies design constraints since it was often placed far from the DRAM pads and thus requiring a LOC constraint to avoid timing violations. The software has to use the following sdram_write_leveling_rst_delay function: static void sdram_write_leveling_rst_delay(int module) { /* Select module */ ddrphy_dly_sel_write(1 << module); /* Reset DQ delay */ ddrphy_wdly_dq_rst_write(1); /* Reset DQS delay */ while (ddrphy_wdly_dqs_inc_count_read() != 0) { ddrphy_wdly_dqs_inc_write(1); cdelay(100); } /* Un-select module */ ddrphy_dly_sel_write(0); }
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- 02 Mar, 2021 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 01 Mar, 2021 2 commits
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Florent Kermarrec authored
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enjoy-digital authored
Add module name CLI option
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- 21 Feb, 2021 1 commit
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Craig Bishop authored
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- 16 Feb, 2021 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
phy/usddrphy: use ic reset (to be sure to follow UG571's reset sequence) and use VAR_LOAD mode on DQS's ODELAYE3. This fixes some reset issues seen on some boards (seen when deployed on large systems with > 100 different boards/controllers), and avoid having to reload DQS delay from software on DQS reset.
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- 05 Feb, 2021 1 commit
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Florent Kermarrec authored
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- 02 Feb, 2021 2 commits
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enjoy-digital authored
init: make the write leveling MR bit configurable
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enjoy-digital authored
Allow to pass all module timings in the format (ck, ns)
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- 30 Jan, 2021 2 commits
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enjoy-digital authored
test: improve error messages when comparing files in test_init.py
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enjoy-digital authored
Add customizable standalone user port data widths
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- 29 Jan, 2021 6 commits
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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Florent Kermarrec authored
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- 28 Jan, 2021 2 commits
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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- 27 Jan, 2021 2 commits
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Florent Kermarrec authored
phy/ecp5ddrphy: add clk_polarity parameter to allow inverting clk polarity (for boards with clk_p/n swapped).
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enjoy-digital authored
modules: add IS43TR16256A support.
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- 25 Jan, 2021 2 commits
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Florent Kermarrec authored
phy/ecp5ddrphy: remove dm_remapping introduce for VexRiscv-SMP on OrangeCrab: we can now use Wishbone/L2.
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Craig Bishop authored
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- 22 Jan, 2021 2 commits
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Gary Wong authored
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Florent Kermarrec authored
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- 21 Jan, 2021 1 commit
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Florent Kermarrec authored
phy/usddrphy: simplify tCK reference by using a specific ODELAYE3 in FIXED mode and keep the PHY in reset by default. Keeping the PHY in reset by default was not possible previously due to the ODELAYE3 configuration that was lost on reset. Using a specific ODELAYE3 in FIXED mode allow keeping the PHY in reset at startup.
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- 12 Jan, 2021 3 commits
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Florent Kermarrec authored
Allow adding a delay on Clock/Commands. Delay is manual for now but could be automated in the future if useful (as done on 7-series/Ultrascale(+)).
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 04 Jan, 2021 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
One some hardware, forcing cl or/and cwl to non-default values can provide better results.
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