platforms/targets: switch to LiteX-Boards.

bench/genesys2.py

@@ -11,7 +11,7 @@ import argparse
 
 from migen import *
 
-from litex.boards.platforms import genesys2
+from litex_boards.platforms import genesys2
 
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *

bench/kc705.py

@@ -11,7 +11,7 @@ import argparse
 
 from migen import *
 
-from litex.boards.platforms import kc705
+from litex_boards.platforms import kc705
 
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *

bench/kcu105.py

@@ -12,7 +12,7 @@ import argparse
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.boards.platforms import kcu105
+from litex_boards.platforms import kcu105
 
 from litex.soc.cores.clock import *
 from litex.soc.interconnect.csr import *

test/test_init.py

@@ -22,7 +22,7 @@ def compare_with_reference(content, filename):
 
 class TestInit(unittest.TestCase):
     def test_sdr(self):
-        from litex.boards.targets.minispartan6 import BaseSoC
+        from litex_boards.targets.minispartan6 import BaseSoC
         soc       = BaseSoC()
         c_header  = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
         py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
@@ -30,7 +30,7 @@ class TestInit(unittest.TestCase):
         self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True)
 
     def test_ddr3(self):
-        from litex.boards.targets.kc705 import BaseSoC
+        from litex_boards.targets.kc705 import BaseSoC
         soc       = BaseSoC()
         c_header  = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
         py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
@@ -38,7 +38,7 @@ class TestInit(unittest.TestCase):
         self.assertEqual(compare_with_reference(py_header, "ddr3_init.py"), True)
 
     def test_ddr4(self):
-        from litex.boards.targets.kcu105 import BaseSoC
+        from litex_boards.targets.kcu105 import BaseSoC
         soc       = BaseSoC(max_sdram_size=0x4000000)
         c_header  = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
         py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)