phy/s7ddrphy: add 1866MT/s support.

litedram/common.py

@@ -42,6 +42,7 @@ def get_default_cl_cwl(memtype, tck):
         f_to_cl_cwl[1066e6] = ( 7, 6)
         f_to_cl_cwl[1333e6] = (10, 7)
         f_to_cl_cwl[1600e6] = (11, 8)
+        f_to_cl_cwl[1866e6] = (13, 9)
     elif memtype == "DDR4":
         f_to_cl_cwl[1333e6] = (9,   9)
         f_to_cl_cwl[1600e6] = (11,  9)

litedram/phy/s7ddrphy.py

@@ -7,7 +7,7 @@
 
 # 1:4, 1:2 frequency-ratio DDR2/DDR3 PHY for Xilinx's Series7
 # DDR2: 400, 533, 667, 800 and 1066 MT/s
-# DDR3: 800, 1066, 1333 and 1600 MT/s
+# DDR3: 800, 1066, 1333 , 1600 and 1866 MT/s
 
 from functools import reduce
 from operator import or_