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litedram
Commit ba0b2263 authored by Florent Kermarrec's avatar Florent Kermarrec
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phy/usddrphy: use ic reset (to be sure to follow UG571's reset sequence) and... 

phy/usddrphy: use ic reset (to be sure to follow UG571's reset sequence) and use VAR_LOAD mode on DQS's ODELAYE3.

This fixes some reset issues seen on some boards (seen when deployed on large systems with > 100 different boards/controllers),
and avoid having to reload DQS delay from software on DQS reset.
parent 080948d4
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Showing with 24 additions and 22 deletions
litedram/phy/usddrphy.py
View file @ ba0b2263
......@@ -59,7 +59,7 @@ class USDDRPHY(Module, AutoCSR):
wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl + cmd_latency)
# Registers --------------------------------------------------------------------------------
self._rst = CSRStorage(reset=1)
self._rst = CSRStorage()
self._en_vtc = CSRStorage(reset=1)
......@@ -134,7 +134,7 @@ class USDDRPHY(Module, AutoCSR):
p_DELAY_TYPE = "FIXED",
p_DELAY_VALUE = int(tck*1e12/4),
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_EN_VTC = 1,
o_CNTVALUEOUT = self._half_sys8x_taps.status,
)
......@@ -153,7 +153,7 @@ class USDDRPHY(Module, AutoCSR):
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal() | self._rst.storage,
i_RST = ResetSignal("ic") | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = 0b10101010,
......@@ -167,7 +167,7 @@ class USDDRPHY(Module, AutoCSR):
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = self._cdly_rst.re | self._rst.storage,
i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
......@@ -214,7 +214,7 @@ class USDDRPHY(Module, AutoCSR):
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal() | self._rst.storage,
i_RST = ResetSignal("ic") | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = Cat(*[getattr(dfi.phases[n//2], dfi_name)[i] for n in range(8)]),
......@@ -228,7 +228,7 @@ class USDDRPHY(Module, AutoCSR):
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = self._cdly_rst.re | self._rst.storage,
i_RST = ResetSignal("ic") | self._cdly_rst.re | self._rst.storage,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
......@@ -280,7 +280,7 @@ class USDDRPHY(Module, AutoCSR):
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal() | self._rst.storage,
i_RST = ResetSignal("ic") | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_T = ~dqs_oe_delay.output,
......@@ -296,15 +296,17 @@ class USDDRPHY(Module, AutoCSR):
p_IS_CLK_INVERTED = 0,
p_IS_RST_INVERTED = 0,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = int(tck*1e12/4),
i_RST = (self._dly_sel.storage[i] & self._wdly_dqs_rst.re) | self._rst.storage,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re,
i_INC = 1,
i_ODATAIN = dqs_nodelay,
o_DATAOUT = dqs_delayed,
p_DELAY_TYPE = "VAR_LOAD",
p_DELAY_VALUE = 0,
i_RST = ResetSignal("ic") | self._rst.storage,
i_LOAD = self._dly_sel.storage[i] & self._wdly_dqs_rst.re,
i_CNTVALUEIN = self._half_sys8x_taps.status,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re,
i_INC = 1,
i_ODATAIN = dqs_nodelay,
o_DATAOUT = dqs_delayed,
),
Instance("IOBUFDSE3",
i_I = dqs_delayed,
......@@ -335,7 +337,7 @@ class USDDRPHY(Module, AutoCSR):
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal() | self._rst.storage,
i_RST = ResetSignal("ic") | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = dm_o_bitslip.o,
......@@ -351,7 +353,7 @@ class USDDRPHY(Module, AutoCSR):
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = (self._dly_sel.storage[i] & self._wdly_dq_rst.re) | self._rst.storage,
i_RST = ResetSignal("ic") | (self._dly_sel.storage[i] & self._wdly_dq_rst.re) | self._rst.storage,
i_EN_VTC = self._en_vtc.storage,
i_CLK = ClockSignal(),
i_CE = self._dly_sel.storage[i] & self._wdly_dq_inc.re,
......@@ -385,7 +387,7 @@ class USDDRPHY(Module, AutoCSR):
p_IS_RST_INVERTED = 0,
p_IS_CLK_INVERTED = 0,
p_IS_CLKDIV_INVERTED = 0,
i_RST = ResetSignal() | self._rst.storage,
i_RST = ResetSignal("ic") | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLKDIV = ClockSignal(),
i_D = dq_o_bitslip.o,
......@@ -403,7 +405,7 @@ class USDDRPHY(Module, AutoCSR):
p_IS_CLK_INVERTED = 0,
p_IS_CLK_B_INVERTED = 1,
p_DATA_WIDTH = 8,
i_RST = ResetSignal(),
i_RST = ResetSignal("ic") | self._rst.storage,
i_CLK = ClockSignal("sys4x"),
i_CLK_B = ClockSignal("sys4x"), # locally inverted
i_CLKDIV = ClockSignal(),
......@@ -423,7 +425,7 @@ class USDDRPHY(Module, AutoCSR):
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = (self._dly_sel.storage[i//8] & self._wdly_dq_rst.re) | self._rst.storage,
i_RST = ResetSignal("ic") | (self._dly_sel.storage[i//8] & self._wdly_dq_rst.re) | self._rst.storage,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._dly_sel.storage[i//8] & self._wdly_dq_inc.re,
......@@ -442,7 +444,7 @@ class USDDRPHY(Module, AutoCSR):
p_DELAY_SRC = "IDATAIN",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = (self._dly_sel.storage[i//8] & self._rdly_dq_rst.re) | self._rst.storage,
i_RST = ResetSignal("ic") | (self._dly_sel.storage[i//8] & self._rdly_dq_rst.re) | self._rst.storage,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
......
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