init: make the write leveling MR bit configurable

litedram/init.py

@@ -220,7 +220,7 @@ def get_ddr3_phy_init_sequence(phy_settings, timing_settings):
         ("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
     ]
 
-    return init_sequence, mr1
+    return init_sequence, {1: mr1}
 
 # DDR4 ---------------------------------------------------------------------------------------------
 
@@ -443,7 +443,7 @@ def get_ddr4_phy_init_sequence(phy_settings, timing_settings):
         ("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
     ]
 
-    return init_sequence, mr1
+    return init_sequence, {1: mr1}
 
 # Init Sequence ------------------------------------------------------------------------------------
 
@@ -568,11 +568,13 @@ const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {{
 """.format(sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
     r += "\n"
 
-    init_sequence, mr1 = get_sdram_phy_init_sequence(phy_settings, timing_settings)
+    init_sequence, mr = get_sdram_phy_init_sequence(phy_settings, timing_settings)
 
     if phy_settings.memtype in ["DDR3", "DDR4"]:
-        # The value of MR1 needs to be modified during write leveling
-        r += "#define DDRX_MR1 {}\n\n".format(mr1)
+        # The value of MR1[7] needs to be modified during write leveling
+        r += "#define DDRX_MR_WRLVL_ADDRESS {}\n\n".format(1)
+        r += "#define DDRX_MR_WRLVL_RESET {}\n\n".format(mr[1])
+        r += "#define DDRX_MR_WRLVL_BIT {}\n\n".format(7)
 
     r += "static void init_sequence(void)\n{\n"
     for comment, a, ba, cmd, delay in init_sequence: