GitLab

clarity on configuration.

The existing VUART interrupt handler did not function
as intended.  Rewrite to match the hardware interfaces.

FSI interface seems stable at this point, and the debug spew to
console is not particularly useful for future development of the
BMC firmware.

Note that this embeds a power limit, which may be board/system specific.

This resolves IPL failures with the current FPGA images

This resolves issues where the #ifdef-controlled code could
counter-intuitively be activated even when the controlling #define
statement was set to 0.

This optional debug mode will attempt to read each Flash chunk three
times, comparing all three read values to determine if bus instability
exists.  This mode is slower than a straight read, but is useful in
initial bringup of new hardware designs or when modifying the SPI
core HDL and for CI/CD checks.

This updates the jenkins configuration to match the recommendations from
https://github.com/jenkinsci/gitlab-plugin

bootrom: Revup bootrom submodule

See merge request !1

- Add common routines for cpu0/cpu1
- Wrap CPU1 code in #ifdef I3CMASTER2_BASE in teh event that the FPGA was not build with the additioanl i2c master.

- Fix description for 64MB flash chips to be 512Mb not 512MB
- Add Support for the 128MB flash chips

Previously, back to back FSI transactions could happen before teh FSI state machine was complete.
This ensures that the FSI master does not ahve an active transaction before starting a new one.

This could result in logs such as:
access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001
access_fsi_mem(): address 0x002804, data: 0x00000000 sta: 0x12000000
vs
access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001
access_fsi_mem(): address 0x002804, data: 0x04c04000 sta: 0x41000001

As a result, the CPU often failed to start.

Major update
Verified to fully IPL attached Blackbird host to Petitboot shell using Versa ECP5