- 05 Mar, 2021 2 commits
-
-
Florent Kermarrec authored
-
Florent Kermarrec authored
-
- 04 Mar, 2021 2 commits
-
-
Florent Kermarrec authored
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
-
Florent Kermarrec authored
-
- 03 Mar, 2021 5 commits
-
-
Florent Kermarrec authored
-
Florent Kermarrec authored
-
Florent Kermarrec authored
-
Florent Kermarrec authored
-
Florent Kermarrec authored
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash https://twitter.com/enjoy_digital/status/1365324823447171074
-
- 25 Feb, 2021 8 commits
-
-
Tim Ansell authored
README.md: fix typo
-
Hans Baier authored
-
enjoy-digital authored
Numato sdcard pmod for Arty
-
enjoy-digital authored
-
Florent Kermarrec authored
-
enjoy-digital authored
Add board support for Terasic/Arrow DECA board (Intel Max10)
-
Hans Baier authored
-
Hans Baier authored
-
- 24 Feb, 2021 3 commits
-
-
enjoy-digital authored
target/arty: add eth_ip_configurable switch
-
Joel Stanley authored
The default stays with the Digilent/Antmicro layout, but the user can optionally provide --sdcard-adaptor numato to use the Numato layout. Signed-off-by: Joel Stanley <joel@jms.id.au>
-
Joel Stanley authored
It has a different layout. Thanks to David for documenting the pinout in this issue: https://github.com/enjoy-digital/litex/issues/817 Expansion Pin SD SPI SD Artix Arty-A7 PMOD PIN PMOD Index 2 DATA_2 D4 JD1 1 0 4 CMD MOSI D3 JD2 2 1 6 DATA_0 MISO F4 JD3 3 2 CD F3 JD4 4 3 1 DATA_3 CS_N E2 JD7 7 4 3 CLK CLK D2 JD8 8 5 5 DATA_1 H2 JD9 9 6 G2 JD10 Signed-off-by: Joel Stanley <joel@jms.id.au>
-
- 23 Feb, 2021 3 commits
-
-
Aleksandra Swierkowska authored
-
Florent Kermarrec authored
-
enjoy-digital authored
fix vc707 default_clk_period
-
- 22 Feb, 2021 1 commit
-
-
- 20 Feb, 2021 2 commits
-
-
Michael Betz authored
-
Michael Betz authored
-
- 18 Feb, 2021 1 commit
-
-
Florent Kermarrec authored
targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.
-
- 16 Feb, 2021 2 commits
-
-
enjoy-digital authored
sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
-
Florent Kermarrec authored
platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks.
-
- 12 Feb, 2021 1 commit
-
-
Florent Kermarrec authored
platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811).
-
- 10 Feb, 2021 1 commit
-
-
Hans Baier authored
-
- 09 Feb, 2021 2 commits
-
-
enjoy-digital authored
vc707.py: clk156 add missing constraint
-
Michael Betz authored
-
- 08 Feb, 2021 1 commit
-
-
Florent Kermarrec authored
-
- 04 Feb, 2021 2 commits
-
-
enjoy-digital authored
arrow_sockit: add support for MiSTer XS SDRAM modules
-
enjoy-digital authored
nexys_video: enable symbiflow toolchain
-
- 03 Feb, 2021 3 commits
-
-
Jan Kowalewski authored
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
-
enjoy-digital authored
targets/colorlight_i5: use .bit stream instead of .svf when loading.
-
Hans Baier authored
-
- 02 Feb, 2021 1 commit
-
-
Kaz Kojima authored
-