Unverified Commit 5b28c619 authored by enjoy-digital's avatar enjoy-digital Committed by GitHub

Merge pull request #178 from yetifrisstlama/vc707_clk

fix vc707 default_clk_period
parents a90c0bc8 09c3bd61
......@@ -629,7 +629,7 @@ _connectors = [
class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 1e9/156.5e6
default_clk_period = 1e9/156.25e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado")
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