Commit 7442c2da authored by Michael Betz's avatar Michael Betz

vc707.py: clk156 add missing constraint

parent fef9dd03
......@@ -642,4 +642,5 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("clk156", loose=True), 1e9/156e6)
self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6)
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment