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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
7442c2da
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Commit
7442c2da
authored
3 years ago
by
Michael Betz
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vc707.py: clk156 add missing constraint
parent
fef9dd03
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litex_boards/platforms/vc707.py
litex_boards/platforms/vc707.py
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litex_boards/platforms/vc707.py
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7442c2da
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...
@@ -642,4 +642,5 @@ class Platform(XilinxPlatform):
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk200"
,
loose
=
True
),
1e9
/
200e6
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk156"
,
loose
=
True
),
1e9
/
156e6
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"sgmii_clock"
,
loose
=
True
),
1e9
/
125e6
)
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