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This provides better timing and faster operation with current Yosys / NextPNR versions

Merge main clock and DVO clock if SoC clock is the same as the
required DVO clock frequency.

Add disabled timings for 1024x768 graphics mode

There have been major changes in the Microwatt CPU core and associated interrupt controller.  These changes now require a rebuild and retest with the PAR seed reset back to 1.

Without this change, the CSR locations are defined by enabled peripheral order,
which produces an unacceptable level of churn in related project device tree
files.

All of the Kestrel firmware and configuration files
fit easily into the on-board Flash of the Arctic Tern
module.  Free up the two socketed Flash devices for
host firmware use.

Enable host UART port

This lowers the CI/CD run time and provides a more repeatable result, especially
since LiteX doesn't produce the same output if the initial ROM contents change.

This FTDI-based interface is also commonly available as a Xilinx-branded "SMT" programmer pod

With the current HDL, attempting to run the system clocks
at 60MHz results in random corruption inside the Tercel
SPI core on at least a handful of ECP5 devices.  As timing
is quite marginal at 60MHz, reduce to 50MHz as an interim
step to increase system stability.

This resolves long-standing issues where the PHY would sometimes
not come online after a power cycle.  Under this failure mode,
the PHY would return 0xffff to all MDIO cycles.  Asserting the
dedicated reset line after powerup appears to correct this fault
condition.

Note that using the MDIO reset command will NOT work under these
circumstances, as the MDIO bus itself is in a failed condition
prior to the external reset pulse.  The MDIO reset command call
has been removed as a result.

Explicitly set the RX skew across all lanes to the known good default

Add production mode command line flag to Arctic Tern target
Build production artifacts along with netboot artifacts

Properly set CPU clock frequency in build script

Explicitly call out Arctic Tern pipeline in CI/CD configuration

Tested with a CPU frequency of 70MHz and a nest frequency of 50MHz

[RCS Arctic tern] Add alternate uses for LPC header signals