Unverified Commit 52d5787a authored by enjoy-digital's avatar enjoy-digital Committed by GitHub

Merge pull request #174 from yetifrisstlama/vc707_clk

vc707.py: clk156 add missing constraint
parents fef9dd03 7442c2da
......@@ -642,4 +642,5 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("clk156", loose=True), 1e9/156e6)
self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6)
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