Merge pull request #174 from yetifrisstlama/vc707_clk

vc707.py: clk156 add missing constraint

Merge pull request #174 from yetifrisstlama/vc707_clk
vc707.py: clk156 add missing constraint
52d5787a · enjoy-digital · GitHub · fef9dd03 · 7442c2da · 52d5787a
Unverified Commit 52d5787a authored Feb 09, 2021 by enjoy-digital Committed by GitHub Feb 09, 2021
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litex_boards/platforms/vc707.py litex_boards/platforms/vc707.py +1 -0

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--- a/litex_boards/platforms/vc707.py
+++ b/litex_boards/platforms/vc707.py
@@ -642,4 +642,5 @@ class Platform(XilinxPlatform):
    def do_finalize(self, fragment):
        XilinxPlatform.do_finalize(self, fragment)
        self.add_period_constraint(self.lookup_request("clk200",      loose=True), 1e9/200e6)
+        self.add_period_constraint(self.lookup_request("clk156",      loose=True), 1e9/156e6)
        self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6)