- 26 May, 2019 2 commits
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Tim Ansell authored
litex/boards/targets: don't use tab for indentation
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Antony Pavlov authored
Fix pep8 E101 "indentation contains mixed spaces and tab" error. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
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- 25 May, 2019 4 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 24 May, 2019 5 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it)
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enjoy-digital authored
Experimental Support for 64-bit RocketChip
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- 23 May, 2019 4 commits
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Gabriel L. Somlo authored
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog, however in the long term it would perhaps be better if enjoy-digital hosted the generated-verilog repository. Once that's in place, I'd be happy to re-spin (and squash) this patch on top of its parent -- GLS
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Gabriel L. Somlo authored
Simulate a Rocket-based 64-bit LiteX SoC with the following command: litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr (with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at this time does not yet properly initialize physical on-board DRAM. On ecp5versa, using '--with-ethernet', up to 97% of the available TRELLIS_SLICE capacity is utilized. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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enjoy-digital authored
tools/litex_sim: restore functionality of '--with-sdram' option
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Gabriel L. Somlo authored
After LiteDRAM commit #50e1d478, an additional positional argument ('databits') is required by the PhySettings() constructor. The value used here (32) will generate a 64MByte simulated SDRAM.
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- 21 May, 2019 3 commits
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enjoy-digital authored
Use 0x43/0xc3 for USB bridge magic packet
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Sean Cross authored
When we get an error with errno 13, it means that the user doesn't have access to the USB device. Rather than silently eating this error and returning -1, print out a message to aid in debugging. Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross authored
The previous value -- 0xc0 -- is used by Windows all the time to query special descriptors. This was causing a conflict when using the USB bridge on a Windows device. Change the magic packet from "Vendor: Device" queries to "Vendor: Other" by setting the bottom two bits. Signed-off-by: Sean Cross <sean@xobs.io>
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- 17 May, 2019 3 commits
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Florent Kermarrec authored
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enjoy-digital authored
boards/nexys4ddr: ethernet support fix-up
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Gabriel L. Somlo authored
Commit 5f6e7874 added ethernet support, let's now also expose it via the "--with-ethernet" command line argument.
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- 16 May, 2019 2 commits
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Florent Kermarrec authored
This could be useful in specific case were we don't have a wishbone master but just want to have a csr bus and allow the user to define it. /!\ Since there is no arbitration on between the CSR masters, use this with precaution /!\
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- 15 May, 2019 1 commit
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Florent Kermarrec authored
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- 14 May, 2019 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 13 May, 2019 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 11 May, 2019 4 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
Cordic is useful for DSP cores but not as a Soc building block.
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Florent Kermarrec authored
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Florent Kermarrec authored
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI support and it also cover what axi_lite was doing: To create a AXILite to CSR bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus directly to the wishbone bus as done in the others non-AXI SoC.
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- 10 May, 2019 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy
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Florent Kermarrec authored
For some designs with different capabilities, we want to run the same software and then have the CSRs/Interrupts defined to a specific location.
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- 09 May, 2019 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
Similar refactor than on interrupts. Adds a add_csr method but still retro-compatible with old way to declare CSRs.
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