- 13 Jan, 2020 1 commit
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Mark authored
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- 10 Jan, 2020 1 commit
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Florent Kermarrec authored
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- 09 Jan, 2020 2 commits
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Florent Kermarrec authored
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Marcin Sloniewski authored
At the start output of the pll is not stabilized, which caused malfunctions when used for sys clock domain. Use AsyncResetSynchronizer to start clock domains on pll locked signal.
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- 31 Dec, 2019 4 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer)
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Florent Kermarrec authored
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- 30 Dec, 2019 3 commits
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msloniewski authored
Add VideoSoC build option, based on Frank Buss example.
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msloniewski authored
Use PLL to generate clock for both sys clock domain and clock domain for sdram. Additionally set up clock domain for VGA periph.
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Giammarco Zacheo authored
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- 06 Dec, 2019 1 commit
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Florent Kermarrec authored
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
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- 03 Dec, 2019 1 commit
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Florent Kermarrec authored
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- 30 Oct, 2019 1 commit
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Florent Kermarrec authored
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- 09 Oct, 2019 1 commit
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Florent Kermarrec authored
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- 03 Sep, 2019 1 commit
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Florent Kermarrec authored
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- 01 Sep, 2019 1 commit
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Florent Kermarrec authored
targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
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- 26 Aug, 2019 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 22 Aug, 2019 1 commit
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Arnaud Durand authored
The system clock was driven directly while it should be driven by the PLL.
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- 11 Aug, 2019 1 commit
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DurandA authored
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- 09 Aug, 2019 3 commits
- 12 Jul, 2019 1 commit
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Florent Kermarrec authored
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- 09 Jul, 2019 1 commit
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David Shah authored
Signed-off-by: David Shah <dave@ds0.me>
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- 24 Jun, 2019 1 commit
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Florent Kermarrec authored
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- 10 Jun, 2019 1 commit
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Florent Kermarrec authored
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