Commit 4126ed21 authored by DurandA's avatar DurandA
Browse files

Add X5 clock and PLL to ECP5 Evaluation Board

parent c7444fe1
# This file is Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch> # This file is Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
# License: BSD # License: BSD
import warnings
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer from litex.build.lattice.programmer import LatticeProgrammer
...@@ -33,10 +31,6 @@ _io = [ ...@@ -33,10 +31,6 @@ _io = [
("user_dip_btn", 8, Pins("A16"), IOStandard("LVCMOS25")), ("user_dip_btn", 8, Pins("A16"), IOStandard("LVCMOS25")),
("serial", 0, ("serial", 0,
Subsignal("rx", Pins("P18"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("N20"), IOStandard("LVCMOS33")),
),
("serial", 1,
Subsignal("rx", Pins("P2"), IOStandard("LVCMOS33")), Subsignal("rx", Pins("P2"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("P3"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("P3"), IOStandard("LVCMOS33")),
), ),
...@@ -47,6 +41,7 @@ _io = [ ...@@ -47,6 +41,7 @@ _io = [
IOStandard("LVDS") IOStandard("LVDS")
), ),
("ext_clk50", 0, Pins("B11"), IOStandard("LVCMOS33")), ("ext_clk50", 0, Pins("B11"), IOStandard("LVCMOS33")),
("ext_clk50_en", 0, Pins("C11"), IOStandard("LVCMOS33")),
] ]
# Connectors --------------------------------------------------------------------------------------- # Connectors ---------------------------------------------------------------------------------------
...@@ -117,16 +112,18 @@ _connectors = [ ...@@ -117,16 +112,18 @@ _connectors = [
class Platform(LatticePlatform): class Platform(LatticePlatform):
default_clk_name = "clk12" default_clk_name = "clk12"
default_clk_period = 83.33 default_clk_period = 1e9/12e6
def __init__(self, **kwargs): def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG381", _io, _connectors, **kwargs) LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG381", _io, _connectors, **kwargs)
def request(self, *args, **kwargs): def request(self, *args, **kwargs):
if "serial" in args: if "serial" in args:
warnings.warn("two 0 Ω resistors shoud be populated on R34 and R35") print("two 0 Ω resistors shoud be populated on R34 and R35 and "
"the FT2232H should be configured to UART with virtual COM on "
"port B")
if "ext_clk50" in args: if "ext_clk50" in args:
warnings.warn("an oscillator must be populated on X5") print("an oscillator must be populated on X5")
return LatticePlatform.request(self, *args, **kwargs) return LatticePlatform.request(self, *args, **kwargs)
......
...@@ -4,7 +4,6 @@ ...@@ -4,7 +4,6 @@
# License: BSD # License: BSD
import argparse import argparse
from warnings import warn
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
...@@ -18,7 +17,7 @@ from litex.soc.integration.builder import * ...@@ -18,7 +17,7 @@ from litex.soc.integration.builder import *
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq, x5_clk_freq):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
# # # # # #
...@@ -26,29 +25,33 @@ class _CRG(Module): ...@@ -26,29 +25,33 @@ class _CRG(Module):
self.cd_sys.clk.attr.add("keep") self.cd_sys.clk.attr.add("keep")
# clk / rst # clk / rst
clk12 = platform.request("clk12") clk = clk12 = platform.request("clk12")
rst_n = platform.request("rst_n") rst_n = platform.request("rst_n")
platform.add_period_constraint(clk12, 83.33) platform.add_period_constraint(clk12, 1e9/12e6)
if x5_clk_freq is not None:
clk = clk50 = platform.request("ext_clk50")
self.comb += platform.request("ext_clk50_en").eq(1)
platform.add_period_constraint(clk50, 1e9/x5_clk_freq)
# pll # pll
# self.submodules.pll = pll = ECP5PLL() self.submodules.pll = pll = ECP5PLL()
# self.comb += pll.reset.eq(~rst_n) self.comb += pll.reset.eq(~rst_n)
# pll.register_clkin(clk12, 12e6) pll.register_clkin(clk, x5_clk_freq or 12e6)
# pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
# self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n) self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
self.comb += self.cd_sys.clk.eq(clk12) self.comb += self.cd_sys.clk.eq(clk)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(12e6), toolchain="diamond", **kwargs): def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="diamond", **kwargs):
platform = ecp5_evn.Platform(toolchain=toolchain) platform = ecp5_evn.Platform(toolchain=toolchain)
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000, integrated_rom_size=0x8000,
**kwargs) **kwargs)
# crg # crg
crg = _CRG(platform, sys_clk_freq) crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
self.submodules.crg = crg self.submodules.crg = crg
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
...@@ -59,12 +62,17 @@ def main(): ...@@ -59,12 +62,17 @@ def main():
help='gateware toolchain to use, diamond (default) or trellis') help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
parser.add_argument("--sys-clk-freq", default=12e6, parser.add_argument("--sys-clk-freq", default=50e6,
help="system clock frequency (default=50MHz)") help="system clock frequency (default=50MHz)")
parser.add_argument("--x5-clk-freq", type=int,
help="use X5 oscillator as system clock at the specified frequency")
args = parser.parse_args() args = parser.parse_args()
cls = BaseSoC cls = BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_core_argdict(args)) soc = cls(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
x5_clk_freq=args.x5_clk_freq,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()
......
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