- 13 Jan, 2020 1 commit
-
-
Mark authored
-
- 09 Jan, 2020 1 commit
-
-
Florent Kermarrec authored
-
- 07 Jan, 2020 1 commit
-
-
Arnaud Durand authored
-
- 31 Dec, 2019 2 commits
-
-
Florent Kermarrec authored
-
Florent Kermarrec authored
-
- 30 Dec, 2019 3 commits
-
-
msloniewski authored
Use single image with memory initialization to make more space for SoC ROM sector.
-
msloniewski authored
V10 and W10 pins were used in UART periph, causing error when gpio_0 were requested.
-
Giammarco Zacheo authored
-
- 06 Nov, 2019 1 commit
-
-
Florent Kermarrec authored
-
- 03 Sep, 2019 1 commit
-
-
Florent Kermarrec authored
-
- 26 Aug, 2019 1 commit
-
-
Florent Kermarrec authored
-
- 11 Aug, 2019 1 commit
-
-
DurandA authored
-
- 09 Aug, 2019 3 commits
- 07 Aug, 2019 1 commit
-
-
Florent Kermarrec authored
- use 1e9/freq for default_clk_period - add default serial on tinyfpga_bx - use S6PLL on minispartan6 - add SPIFlash pins on versa_ecp5
-
- 12 Jul, 2019 1 commit
-
-
Florent Kermarrec authored
-
- 09 Jul, 2019 1 commit
-
-
David Shah authored
Signed-off-by: David Shah <dave@ds0.me>
-
- 24 Jun, 2019 1 commit
-
-
Florent Kermarrec authored
-
- 10 Jun, 2019 1 commit
-
-
Florent Kermarrec authored
-