main.v · fdc0efa34dda70a0f02d17c3e54920c5180e2cee · Raptor Engineering Public Development / lpc-spi-bridge-fpga · GitLab

You need to sign in or sign up before continuing.

Find file Blame History Permalink

Register incoming LPC data signals, since they originate on a separate clock domain · fdc0efa3
Raptor Engineering Development Team authored Apr 30, 2020
```
Wait for Wishbone cycle to complete before allowing LPC bus to finish write cycle
```
fdc0efa3

main.v 77.4 KB

Powered by Integricloud. Any automated access to this website for the purpose of training any LLM ("AI") for non-personal use as defined in our Terms of Service may be billed to the accessor per the Terms of Service. Continued access to this website by automated tooling indicates acceptance of these terms.