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This required inserting a wait state after every RAM read address update,
due to the data not reliably appearing on the read port until two clocks
after the address is set.  The iCE40 EBR blocks are poorly documented;
there is some evidence they act as if the output is registered even though
it is not officially stated as such.  Due to the lack of official documentation
combined with observed behavior, pipelining on the read ports was considered too
risky for the benefit gained.