-
Raptor Engineering Development Team authored
With the latest HDL changes, signal integrity is maintained at 33MHz. Use the full 33MHz clock to drive both the sequencer state machines and the SPI core.
02a9509f
With the latest HDL changes, signal integrity is maintained at 33MHz. Use the full 33MHz clock to drive both the sequencer state machines and the SPI core.
Powered by Integricloud