main.v · 02a9509fa5c51440d763287aecd1775c0203b48a · Raptor Engineering Public Development / lpc-spi-bridge-fpga

Use full speed LPC clock as sequencer clock · 02a9509f

Raptor Engineering Development Team authored Apr 17, 2020

With the latest HDL changes, signal integrity is maintained at 33MHz.
Use the full 33MHz clock to drive both the sequencer state machines
and the SPI core.

02a9509f

main.v 72.3 KB

Replace main.v