intel_ddi.c 61 KB
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/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eugeni Dodonov <eugeni.dodonov@intel.com>
 *
 */

#include "i915_drv.h"
#include "intel_drv.h"

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struct ddi_buf_trans {
	u32 trans1;	/* balance leg enable, de-emph level */
	u32 trans2;	/* vref sel, vswing */
};

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/* HDMI/DVI modes ignore everything but the last 2 items. So we share
 * them for both DP and FDI transports, allowing those ports to
 * automatically adapt to HDMI connections as well
 */
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static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
	{ 0x00FFFFFF, 0x0006000E },
	{ 0x00D75FFF, 0x0005000A },
	{ 0x00C30FFF, 0x00040006 },
	{ 0x80AAAFFF, 0x000B0000 },
	{ 0x00FFFFFF, 0x0005000A },
	{ 0x00D75FFF, 0x000C0004 },
	{ 0x80C30FFF, 0x000B0000 },
	{ 0x00FFFFFF, 0x00040006 },
	{ 0x80D75FFF, 0x000B0000 },
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};

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static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
	{ 0x00FFFFFF, 0x0007000E },
	{ 0x00D75FFF, 0x000F000A },
	{ 0x00C30FFF, 0x00060006 },
	{ 0x00AAAFFF, 0x001E0000 },
	{ 0x00FFFFFF, 0x000F000A },
	{ 0x00D75FFF, 0x00160004 },
	{ 0x00C30FFF, 0x001E0000 },
	{ 0x00FFFFFF, 0x00060006 },
	{ 0x00D75FFF, 0x001E0000 },
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};

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static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
					/* Idx	NT mV d	T mV d	db	*/
	{ 0x00FFFFFF, 0x0006000E },	/* 0:	400	400	0	*/
	{ 0x00E79FFF, 0x000E000C },	/* 1:	400	500	2	*/
	{ 0x00D75FFF, 0x0005000A },	/* 2:	400	600	3.5	*/
	{ 0x00FFFFFF, 0x0005000A },	/* 3:	600	600	0	*/
	{ 0x00E79FFF, 0x001D0007 },	/* 4:	600	750	2	*/
	{ 0x00D75FFF, 0x000C0004 },	/* 5:	600	900	3.5	*/
	{ 0x00FFFFFF, 0x00040006 },	/* 6:	800	800	0	*/
	{ 0x80E79FFF, 0x00030002 },	/* 7:	800	1000	2	*/
	{ 0x00FFFFFF, 0x00140005 },	/* 8:	850	850	0	*/
	{ 0x00FFFFFF, 0x000C0004 },	/* 9:	900	900	0	*/
	{ 0x00FFFFFF, 0x001C0003 },	/* 10:	950	950	0	*/
	{ 0x80FFFFFF, 0x00030002 },	/* 11:	1000	1000	0	*/
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};

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static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
	{ 0x00FFFFFF, 0x00000012 },
	{ 0x00EBAFFF, 0x00020011 },
	{ 0x00C71FFF, 0x0006000F },
	{ 0x00AAAFFF, 0x000E000A },
	{ 0x00FFFFFF, 0x00020011 },
	{ 0x00DB6FFF, 0x0005000F },
	{ 0x00BEEFFF, 0x000A000C },
	{ 0x00FFFFFF, 0x0005000F },
	{ 0x00DB6FFF, 0x000A000C },
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};

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static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
	{ 0x00FFFFFF, 0x0007000E },
	{ 0x00D75FFF, 0x000E000A },
	{ 0x00BEFFFF, 0x00140006 },
	{ 0x80B2CFFF, 0x001B0002 },
	{ 0x00FFFFFF, 0x000E000A },
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	{ 0x00DB6FFF, 0x00160005 },
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	{ 0x80C71FFF, 0x001A0002 },
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	{ 0x00F7DFFF, 0x00180004 },
	{ 0x80D75FFF, 0x001B0002 },
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};

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static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
	{ 0x00FFFFFF, 0x0001000E },
	{ 0x00D75FFF, 0x0004000A },
	{ 0x00C30FFF, 0x00070006 },
	{ 0x00AAAFFF, 0x000C0000 },
	{ 0x00FFFFFF, 0x0004000A },
	{ 0x00D75FFF, 0x00090004 },
	{ 0x00C30FFF, 0x000C0000 },
	{ 0x00FFFFFF, 0x00070006 },
	{ 0x00D75FFF, 0x000C0000 },
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};

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static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
					/* Idx	NT mV d	T mV df	db	*/
	{ 0x00FFFFFF, 0x0007000E },	/* 0:	400	400	0	*/
	{ 0x00D75FFF, 0x000E000A },	/* 1:	400	600	3.5	*/
	{ 0x00BEFFFF, 0x00140006 },	/* 2:	400	800	6	*/
	{ 0x00FFFFFF, 0x0009000D },	/* 3:	450	450	0	*/
	{ 0x00FFFFFF, 0x000E000A },	/* 4:	600	600	0	*/
	{ 0x00D7FFFF, 0x00140006 },	/* 5:	600	800	2.5	*/
	{ 0x80CB2FFF, 0x001B0002 },	/* 6:	600	1000	4.5	*/
	{ 0x00FFFFFF, 0x00140006 },	/* 7:	800	800	0	*/
	{ 0x80E79FFF, 0x001B0002 },	/* 8:	800	1000	2	*/
	{ 0x80FFFFFF, 0x001B0002 },	/* 9:	1000	1000	0	*/
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};

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static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
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	{ 0x00000018, 0x000000a2 },
	{ 0x00004014, 0x0000009B },
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	{ 0x00006012, 0x00000088 },
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	{ 0x00008010, 0x00000087 },
	{ 0x00000018, 0x0000009B },
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	{ 0x00004014, 0x00000088 },
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	{ 0x00006012, 0x00000087 },
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	{ 0x00000018, 0x00000088 },
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	{ 0x00004014, 0x00000087 },
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};

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/* eDP 1.4 low vswing translation parameters */
static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
	{ 0x00000018, 0x000000a8 },
	{ 0x00002016, 0x000000ab },
	{ 0x00006012, 0x000000a2 },
	{ 0x00008010, 0x00000088 },
	{ 0x00000018, 0x000000ab },
	{ 0x00004014, 0x000000a2 },
	{ 0x00006012, 0x000000a6 },
	{ 0x00000018, 0x000000a2 },
	{ 0x00005013, 0x0000009c },
	{ 0x00000018, 0x00000088 },
};


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static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
					/* Idx	NT mV   T mV    db  */
	{ 0x00000018, 0x000000a0 },	/* 0:	400	400	0   */
	{ 0x00004014, 0x00000098 },	/* 1:	400	600	3.5 */
	{ 0x00006012, 0x00000088 },	/* 2:	400	800	6   */
	{ 0x00000018, 0x0000003c },	/* 3:	450	450	0   */
	{ 0x00000018, 0x00000098 },	/* 4:	600	600	0   */
	{ 0x00003015, 0x00000088 },	/* 5:	600	800	2.5 */
	{ 0x00005013, 0x00000080 },	/* 6:	600	1000	4.5 */
	{ 0x00000018, 0x00000088 },	/* 7:	800	800	0   */
	{ 0x00000096, 0x00000080 },	/* 8:	800	1000	2   */
	{ 0x00000018, 0x00000080 },	/* 9:	1200	1200	0   */
};

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enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
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{
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	struct drm_encoder *encoder = &intel_encoder->base;
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	int type = intel_encoder->type;

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	if (type == INTEL_OUTPUT_DP_MST) {
		struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
		return intel_dig_port->port;
	} else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
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	    type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
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		struct intel_digital_port *intel_dig_port =
			enc_to_dig_port(encoder);
		return intel_dig_port->port;
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	} else if (type == INTEL_OUTPUT_ANALOG) {
		return PORT_E;
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	} else {
		DRM_ERROR("Invalid DDI encoder type %d\n", type);
		BUG();
	}
}

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/*
 * Starting with Haswell, DDI port buffers must be programmed with correct
 * values in advance. The buffer values are different for FDI and DP modes,
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 * but the HDMI/DVI fields are shared among those. So we program the DDI
 * in either FDI or DP modes only, as HDMI connections will work with both
 * of those
 */
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static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg;
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	int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_800mV_0dB,
	    size;
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	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
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	const struct ddi_buf_trans *ddi_translations_fdi;
	const struct ddi_buf_trans *ddi_translations_dp;
	const struct ddi_buf_trans *ddi_translations_edp;
	const struct ddi_buf_trans *ddi_translations_hdmi;
	const struct ddi_buf_trans *ddi_translations;
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	if (IS_SKYLAKE(dev)) {
		ddi_translations_fdi = NULL;
		ddi_translations_dp = skl_ddi_translations_dp;
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		n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
		if (dev_priv->vbt.edp_low_vswing) {
			ddi_translations_edp = skl_ddi_translations_edp;
			n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
		} else {
			ddi_translations_edp = skl_ddi_translations_dp;
			n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
		}

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		ddi_translations_hdmi = skl_ddi_translations_hdmi;
		n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
		hdmi_800mV_0dB = 7;
	} else if (IS_BROADWELL(dev)) {
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		ddi_translations_fdi = bdw_ddi_translations_fdi;
		ddi_translations_dp = bdw_ddi_translations_dp;
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		ddi_translations_edp = bdw_ddi_translations_edp;
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		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
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		n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
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		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
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		hdmi_800mV_0dB = 7;
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	} else if (IS_HASWELL(dev)) {
		ddi_translations_fdi = hsw_ddi_translations_fdi;
		ddi_translations_dp = hsw_ddi_translations_dp;
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		ddi_translations_edp = hsw_ddi_translations_dp;
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		ddi_translations_hdmi = hsw_ddi_translations_hdmi;
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		n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
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		n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
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		hdmi_800mV_0dB = 6;
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	} else {
		WARN(1, "ddi translation table missing\n");
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		ddi_translations_edp = bdw_ddi_translations_dp;
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		ddi_translations_fdi = bdw_ddi_translations_fdi;
		ddi_translations_dp = bdw_ddi_translations_dp;
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		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
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		n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
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		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
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		hdmi_800mV_0dB = 7;
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	}

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	switch (port) {
	case PORT_A:
		ddi_translations = ddi_translations_edp;
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		size = n_edp_entries;
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		break;
	case PORT_B:
	case PORT_C:
		ddi_translations = ddi_translations_dp;
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		size = n_dp_entries;
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		break;
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	case PORT_D:
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		if (intel_dp_is_edp(dev, PORT_D)) {
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			ddi_translations = ddi_translations_edp;
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			size = n_edp_entries;
		} else {
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			ddi_translations = ddi_translations_dp;
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			size = n_dp_entries;
		}
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		break;
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	case PORT_E:
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		if (ddi_translations_fdi)
			ddi_translations = ddi_translations_fdi;
		else
			ddi_translations = ddi_translations_dp;
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		size = n_dp_entries;
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		break;
	default:
		BUG();
	}
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	for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
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		I915_WRITE(reg, ddi_translations[i].trans1);
		reg += 4;
		I915_WRITE(reg, ddi_translations[i].trans2);
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		reg += 4;
	}
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	/* Choose a good default if VBT is badly populated */
	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
	    hdmi_level >= n_hdmi_entries)
		hdmi_level = hdmi_800mV_0dB;

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	/* Entry 9 is for HDMI: */
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	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
	reg += 4;
	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
	reg += 4;
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}

/* Program DDI buffers translations for DP. By default, program ports A-D in DP
 * mode and port E for FDI.
 */
void intel_prepare_ddi(struct drm_device *dev)
{
	int port;

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	if (!HAS_DDI(dev))
		return;
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	for (port = PORT_A; port <= PORT_E; port++)
		intel_prepare_ddi_buffers(dev, port);
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}
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static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
				    enum port port)
{
	uint32_t reg = DDI_BUF_CTL(port);
	int i;

	for (i = 0; i < 8; i++) {
		udelay(1);
		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
			return;
	}
	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
}
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/* Starting with Haswell, different DDI ports can work in FDI mode for
 * connection to the PCH-located connectors. For this, it is necessary to train
 * both the DDI port and PCH receiver for the desired DDI buffer settings.
 *
 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 * please note that when FDI mode is active on DDI E, it shares 2 lines with
 * DDI A (which is used for eDP)
 */

void hsw_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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	u32 temp, i, rx_ctl_val;
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	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
	 * mode set "sequence for CRT port" document:
	 * - TP1 to TP2 time with the default value
	 * - FDI delay to 90h
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	 *
	 * WaFDIAutoLinkSetTimingOverrride:hsw
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	 */
	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
				  FDI_RX_PWRDN_LANE0_VAL(2) |
				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

	/* Enable the PCH Receiver FDI PLL */
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	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
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		     FDI_RX_PLL_ENABLE |
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		     FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
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	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
	POSTING_READ(_FDI_RXA_CTL);
	udelay(220);

	/* Switch from Rawclk to PCDclk */
	rx_ctl_val |= FDI_PCDCLK;
	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);

	/* Configure Port Clock Select */
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	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
	WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
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	/* Start the training iterating through available voltages and emphasis,
	 * testing each value twice. */
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	for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
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		/* Configure DP_TP_CTL with auto-training */
		I915_WRITE(DP_TP_CTL(PORT_E),
					DP_TP_CTL_FDI_AUTOTRAIN |
					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
					DP_TP_CTL_LINK_TRAIN_PAT1 |
					DP_TP_CTL_ENABLE);

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		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
		 * DDI E does not support port reversal, the functionality is
		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
		 * port reversal bit */
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		I915_WRITE(DDI_BUF_CTL(PORT_E),
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			   DDI_BUF_CTL_ENABLE |
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			   ((intel_crtc->config->fdi_lanes - 1) << 1) |
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			   DDI_BUF_TRANS_SELECT(i / 2));
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		POSTING_READ(DDI_BUF_CTL(PORT_E));
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		udelay(600);

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		/* Program PCH FDI Receiver TU */
		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));

		/* Enable PCH FDI Receiver with auto-training */
		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
		POSTING_READ(_FDI_RXA_CTL);

		/* Wait for FDI receiver lane calibration */
		udelay(30);

		/* Unset FDI_RX_MISC pwrdn lanes */
		temp = I915_READ(_FDI_RXA_MISC);
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
		I915_WRITE(_FDI_RXA_MISC, temp);
		POSTING_READ(_FDI_RXA_MISC);

		/* Wait for FDI auto training time */
		udelay(5);
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		temp = I915_READ(DP_TP_STATUS(PORT_E));
		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
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			DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
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			/* Enable normal pixel sending for FDI */
			I915_WRITE(DP_TP_CTL(PORT_E),
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				   DP_TP_CTL_FDI_AUTOTRAIN |
				   DP_TP_CTL_LINK_TRAIN_NORMAL |
				   DP_TP_CTL_ENHANCED_FRAME_ENABLE |
				   DP_TP_CTL_ENABLE);
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			return;
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		}
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		temp = I915_READ(DDI_BUF_CTL(PORT_E));
		temp &= ~DDI_BUF_CTL_ENABLE;
		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
		POSTING_READ(DDI_BUF_CTL(PORT_E));

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		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
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		temp = I915_READ(DP_TP_CTL(PORT_E));
		temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
		I915_WRITE(DP_TP_CTL(PORT_E), temp);
		POSTING_READ(DP_TP_CTL(PORT_E));

		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
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		rx_ctl_val &= ~FDI_RX_ENABLE;
		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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		POSTING_READ(_FDI_RXA_CTL);
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		/* Reset FDI_RX_MISC pwrdn lanes */
		temp = I915_READ(_FDI_RXA_MISC);
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
		I915_WRITE(_FDI_RXA_MISC, temp);
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		POSTING_READ(_FDI_RXA_MISC);
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	}

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	DRM_ERROR("FDI link training failed!\n");
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}
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void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);

	intel_dp->DP = intel_dig_port->saved_port_bits |
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		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
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	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);

}

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static struct intel_encoder *
intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *intel_encoder, *ret = NULL;
	int num_encoders = 0;

	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		ret = intel_encoder;
		num_encoders++;
	}

	if (num_encoders != 1)
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		WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
		     pipe_name(intel_crtc->pipe));
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	BUG_ON(ret == NULL);
	return ret;
}

496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516
static struct intel_encoder *
intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct intel_encoder *intel_encoder, *ret = NULL;
	int num_encoders = 0;

	for_each_intel_encoder(dev, intel_encoder) {
		if (intel_encoder->new_crtc == crtc) {
			ret = intel_encoder;
			num_encoders++;
		}
	}

	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
	     pipe_name(crtc->pipe));

	BUG_ON(ret == NULL);
	return ret;
}

517
#define LC_FREQ 2700
518
#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
519 520 521 522 523 524 525 526 527 528 529

#define P_MIN 2
#define P_MAX 64
#define P_INC 2

/* Constraints for PLL good behavior */
#define REF_MIN 48
#define REF_MAX 400
#define VCO_MIN 2400
#define VCO_MAX 4800

530 531 532 533 534
#define abs_diff(a, b) ({			\
	typeof(a) __a = (a);			\
	typeof(b) __b = (b);			\
	(void) (&__a == &__b);			\
	__a > __b ? (__a - __b) : (__b - __a); })
535 536 537 538 539 540

struct wrpll_rnp {
	unsigned p, n2, r2;
};

static unsigned wrpll_get_budget_for_freq(int clock)
541
{
542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609
	unsigned budget;

	switch (clock) {
	case 25175000:
	case 25200000:
	case 27000000:
	case 27027000:
	case 37762500:
	case 37800000:
	case 40500000:
	case 40541000:
	case 54000000:
	case 54054000:
	case 59341000:
	case 59400000:
	case 72000000:
	case 74176000:
	case 74250000:
	case 81000000:
	case 81081000:
	case 89012000:
	case 89100000:
	case 108000000:
	case 108108000:
	case 111264000:
	case 111375000:
	case 148352000:
	case 148500000:
	case 162000000:
	case 162162000:
	case 222525000:
	case 222750000:
	case 296703000:
	case 297000000:
		budget = 0;
		break;
	case 233500000:
	case 245250000:
	case 247750000:
	case 253250000:
	case 298000000:
		budget = 1500;
		break;
	case 169128000:
	case 169500000:
	case 179500000:
	case 202000000:
		budget = 2000;
		break;
	case 256250000:
	case 262500000:
	case 270000000:
	case 272500000:
	case 273750000:
	case 280750000:
	case 281250000:
	case 286000000:
	case 291750000:
		budget = 4000;
		break;
	case 267250000:
	case 268500000:
		budget = 5000;
		break;
	default:
		budget = 1000;
		break;
	}
610

611 612 613 614 615 616 617 618
	return budget;
}

static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
			     unsigned r2, unsigned n2, unsigned p,
			     struct wrpll_rnp *best)
{
	uint64_t a, b, c, d, diff, diff_best;
619

620 621 622 623 624 625 626
	/* No best (r,n,p) yet */
	if (best->p == 0) {
		best->p = p;
		best->n2 = n2;
		best->r2 = r2;
		return;
	}
627

628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643
	/*
	 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
	 * freq2k.
	 *
	 * delta = 1e6 *
	 *	   abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
	 *	   freq2k;
	 *
	 * and we would like delta <= budget.
	 *
	 * If the discrepancy is above the PPM-based budget, always prefer to
	 * improve upon the previous solution.  However, if you're within the
	 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
	 */
	a = freq2k * budget * p * r2;
	b = freq2k * budget * best->p * best->r2;
644 645 646
	diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
	diff_best = abs_diff(freq2k * best->p * best->r2,
			     LC_FREQ_2K * best->n2);
647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672
	c = 1000000 * diff;
	d = 1000000 * diff_best;

	if (a < c && b < d) {
		/* If both are above the budget, pick the closer */
		if (best->p * best->r2 * diff < p * r2 * diff_best) {
			best->p = p;
			best->n2 = n2;
			best->r2 = r2;
		}
	} else if (a >= c && b < d) {
		/* If A is below the threshold but B is above it?  Update. */
		best->p = p;
		best->n2 = n2;
		best->r2 = r2;
	} else if (a >= c && b >= d) {
		/* Both are below the limit, so pick the higher n2/(r2*r2) */
		if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
			best->p = p;
			best->n2 = n2;
			best->r2 = r2;
		}
	}
	/* Otherwise a < c && b >= d, do nothing */
}

673 674 675 676 677 678 679 680
static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
				     int reg)
{
	int refclk = LC_FREQ;
	int n, p, r;
	u32 wrpll;

	wrpll = I915_READ(reg);
681 682 683
	switch (wrpll & WRPLL_PLL_REF_MASK) {
	case WRPLL_PLL_SSC:
	case WRPLL_PLL_NON_SSC:
684 685 686 687 688 689 690
		/*
		 * We could calculate spread here, but our checking
		 * code only cares about 5% accuracy, and spread is a max of
		 * 0.5% downspread.
		 */
		refclk = 135;
		break;
691
	case WRPLL_PLL_LCPLL:
692 693 694 695 696 697 698 699 700 701 702
		refclk = LC_FREQ;
		break;
	default:
		WARN(1, "bad wrpll refclk\n");
		return 0;
	}

	r = wrpll & WRPLL_DIVIDER_REF_MASK;
	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;

703 704
	/* Convert to KHz, p & r have a fixed point portion */
	return (refclk * n * 100) / (p * r);
705 706
}

707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768
static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
			       uint32_t dpll)
{
	uint32_t cfgcr1_reg, cfgcr2_reg;
	uint32_t cfgcr1_val, cfgcr2_val;
	uint32_t p0, p1, p2, dco_freq;

	cfgcr1_reg = GET_CFG_CR1_REG(dpll);
	cfgcr2_reg = GET_CFG_CR2_REG(dpll);

	cfgcr1_val = I915_READ(cfgcr1_reg);
	cfgcr2_val = I915_READ(cfgcr2_reg);

	p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
	p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;

	if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
		p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
	else
		p1 = 1;


	switch (p0) {
	case DPLL_CFGCR2_PDIV_1:
		p0 = 1;
		break;
	case DPLL_CFGCR2_PDIV_2:
		p0 = 2;
		break;
	case DPLL_CFGCR2_PDIV_3:
		p0 = 3;
		break;
	case DPLL_CFGCR2_PDIV_7:
		p0 = 7;
		break;
	}

	switch (p2) {
	case DPLL_CFGCR2_KDIV_5:
		p2 = 5;
		break;
	case DPLL_CFGCR2_KDIV_2:
		p2 = 2;
		break;
	case DPLL_CFGCR2_KDIV_3:
		p2 = 3;
		break;
	case DPLL_CFGCR2_KDIV_1:
		p2 = 1;
		break;
	}

	dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;

	dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
		1000) / 0x8000;

	return dco_freq / (p0 * p1 * p2 * 5);
}


static void skl_ddi_clock_get(struct intel_encoder *encoder,
769
				struct intel_crtc_state *pipe_config)
770 771 772 773 774
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	int link_clock = 0;
	uint32_t dpll_ctl1, dpll;

775
	dpll = pipe_config->ddi_pll_sel;
776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804

	dpll_ctl1 = I915_READ(DPLL_CTRL1);

	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
		link_clock = skl_calc_wrpll_link(dev_priv, dpll);
	} else {
		link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
		link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);

		switch (link_clock) {
		case DPLL_CRTL1_LINK_RATE_810:
			link_clock = 81000;
			break;
		case DPLL_CRTL1_LINK_RATE_1350:
			link_clock = 135000;
			break;
		case DPLL_CRTL1_LINK_RATE_2700:
			link_clock = 270000;
			break;
		default:
			WARN(1, "Unsupported link rate\n");
			break;
		}
		link_clock *= 2;
	}

	pipe_config->port_clock = link_clock;

	if (pipe_config->has_dp_encoder)
805
		pipe_config->base.adjusted_mode.crtc_clock =
806 807 808
			intel_dotclock_calculate(pipe_config->port_clock,
						 &pipe_config->dp_m_n);
	else
809
		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
810 811
}

812
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
813
			      struct intel_crtc_state *pipe_config)
814 815 816 817 818
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	int link_clock = 0;
	u32 val, pll;

819
	val = pipe_config->ddi_pll_sel;
820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856
	switch (val & PORT_CLK_SEL_MASK) {
	case PORT_CLK_SEL_LCPLL_810:
		link_clock = 81000;
		break;
	case PORT_CLK_SEL_LCPLL_1350:
		link_clock = 135000;
		break;
	case PORT_CLK_SEL_LCPLL_2700:
		link_clock = 270000;
		break;
	case PORT_CLK_SEL_WRPLL1:
		link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
		break;
	case PORT_CLK_SEL_WRPLL2:
		link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
		break;
	case PORT_CLK_SEL_SPLL:
		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
		if (pll == SPLL_PLL_FREQ_810MHz)
			link_clock = 81000;
		else if (pll == SPLL_PLL_FREQ_1350MHz)
			link_clock = 135000;
		else if (pll == SPLL_PLL_FREQ_2700MHz)
			link_clock = 270000;
		else {
			WARN(1, "bad spll freq\n");
			return;
		}
		break;
	default:
		WARN(1, "bad port clock sel\n");
		return;
	}

	pipe_config->port_clock = link_clock * 2;

	if (pipe_config->has_pch_encoder)
857
		pipe_config->base.adjusted_mode.crtc_clock =
858 859 860
			intel_dotclock_calculate(pipe_config->port_clock,
						 &pipe_config->fdi_m_n);
	else if (pipe_config->has_dp_encoder)
861
		pipe_config->base.adjusted_mode.crtc_clock =
862 863 864
			intel_dotclock_calculate(pipe_config->port_clock,
						 &pipe_config->dp_m_n);
	else
865
		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
866 867
}

868
void intel_ddi_clock_get(struct intel_encoder *encoder,
869
			 struct intel_crtc_state *pipe_config)
870
{
871 872 873 874 875 876
	struct drm_device *dev = encoder->base.dev;

	if (INTEL_INFO(dev)->gen <= 8)
		hsw_ddi_clock_get(encoder, pipe_config);
	else
		skl_ddi_clock_get(encoder, pipe_config);
877 878
}

879
static void
880 881
hsw_ddi_calculate_wrpll(int clock /* in Hz */,
			unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937
{
	uint64_t freq2k;
	unsigned p, n2, r2;
	struct wrpll_rnp best = { 0, 0, 0 };
	unsigned budget;

	freq2k = clock / 100;

	budget = wrpll_get_budget_for_freq(clock);

	/* Special case handling for 540 pixel clock: bypass WR PLL entirely
	 * and directly pass the LC PLL to it. */
	if (freq2k == 5400000) {
		*n2_out = 2;
		*p_out = 1;
		*r2_out = 2;
		return;
	}

	/*
	 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
	 * the WR PLL.
	 *
	 * We want R so that REF_MIN <= Ref <= REF_MAX.
	 * Injecting R2 = 2 * R gives:
	 *   REF_MAX * r2 > LC_FREQ * 2 and
	 *   REF_MIN * r2 < LC_FREQ * 2
	 *
	 * Which means the desired boundaries for r2 are:
	 *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
	 *
	 */
	for (r2 = LC_FREQ * 2 / REF_MAX + 1;
	     r2 <= LC_FREQ * 2 / REF_MIN;
	     r2++) {

		/*
		 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
		 *
		 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
		 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
		 *   VCO_MAX * r2 > n2 * LC_FREQ and
		 *   VCO_MIN * r2 < n2 * LC_FREQ)
		 *
		 * Which means the desired boundaries for n2 are:
		 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
		 */
		for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
		     n2 <= VCO_MAX * r2 / LC_FREQ;
		     n2++) {

			for (p = P_MIN; p <= P_MAX; p += P_INC)
				wrpll_update_rnp(freq2k, budget,
						 r2, n2, p, &best);
		}
	}
938

939 940 941
	*n2_out = best.n2;
	*p_out = best.p;
	*r2_out = best.r2;
942 943
}

944
static bool
945
hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
946
		   struct intel_crtc_state *crtc_state,
947 948
		   struct intel_encoder *intel_encoder,
		   int clock)
949
{
950
	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
951
		struct intel_shared_dpll *pll;
952
		uint32_t val;
953
		unsigned p, n2, r2;
954

955
		hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
956

957
		val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
958 959 960
		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
		      WRPLL_DIVIDER_POST(p);

961
		crtc_state->dpll_hw_state.wrpll = val;
962

963
		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
964 965 966 967
		if (pll == NULL) {
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
					 pipe_name(intel_crtc->pipe));
			return false;
968
		}
969

970
		crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
971 972 973 974 975
	}

	return true;
}

976 977 978 979 980 981 982 983 984 985 986 987 988 989 990
struct skl_wrpll_params {
	uint32_t        dco_fraction;
	uint32_t        dco_integer;
	uint32_t        qdiv_ratio;
	uint32_t        qdiv_mode;
	uint32_t        kdiv;
	uint32_t        pdiv;
	uint32_t        central_freq;
};

static void
skl_ddi_calculate_wrpll(int clock /* in Hz */,
			struct skl_wrpll_params *wrpll_params)
{
	uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
991 992 993
	uint64_t dco_central_freq[3] = {8400000000ULL,
					9000000000ULL,
					9600000000ULL};
994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065
	uint32_t min_dco_deviation = 400;
	uint32_t min_dco_index = 3;
	uint32_t P0[4] = {1, 2, 3, 7};
	uint32_t P2[4] = {1, 2, 3, 5};
	bool found = false;
	uint32_t candidate_p = 0;
	uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
	uint32_t candidate_p2[3] = {0};
	uint32_t dco_central_freq_deviation[3];
	uint32_t i, P1, k, dco_count;
	bool retry_with_odd = false;
	uint64_t dco_freq;

	/* Determine P0, P1 or P2 */
	for (dco_count = 0; dco_count < 3; dco_count++) {
		found = false;
		candidate_p =
			div64_u64(dco_central_freq[dco_count], afe_clock);
		if (retry_with_odd == false)
			candidate_p = (candidate_p % 2 == 0 ?
				candidate_p : candidate_p + 1);

		for (P1 = 1; P1 < candidate_p; P1++) {
			for (i = 0; i < 4; i++) {
				if (!(P0[i] != 1 || P1 == 1))
					continue;

				for (k = 0; k < 4; k++) {
					if (P1 != 1 && P2[k] != 2)
						continue;

					if (candidate_p == P0[i] * P1 * P2[k]) {
						/* Found possible P0, P1, P2 */
						found = true;
						candidate_p0[dco_count] = P0[i];
						candidate_p1[dco_count] = P1;
						candidate_p2[dco_count] = P2[k];
						goto found;
					}

				}
			}
		}

found:
		if (found) {
			dco_central_freq_deviation[dco_count] =
				div64_u64(10000 *
					  abs_diff((candidate_p * afe_clock),
						   dco_central_freq[dco_count]),
					  dco_central_freq[dco_count]);

			if (dco_central_freq_deviation[dco_count] <
				min_dco_deviation) {
				min_dco_deviation =
					dco_central_freq_deviation[dco_count];
				min_dco_index = dco_count;
			}
		}

		if (min_dco_index > 2 && dco_count == 2) {
			retry_with_odd = true;
			dco_count = 0;
		}
	}

	if (min_dco_index > 2) {
		WARN(1, "No valid values found for the given pixel clock\n");
	} else {
		 wrpll_params->central_freq = dco_central_freq[min_dco_index];

		 switch (dco_central_freq[min_dco_index]) {
1066
		 case 9600000000ULL:
1067 1068
			wrpll_params->central_freq = 0;
			break;
1069
		 case 9000000000ULL:
1070 1071
			wrpll_params->central_freq = 1;
			break;
1072
		 case 8400000000ULL:
1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132
			wrpll_params->central_freq = 3;
		 }

		 switch (candidate_p0[min_dco_index]) {
		 case 1:
			wrpll_params->pdiv = 0;
			break;
		 case 2:
			wrpll_params->pdiv = 1;
			break;
		 case 3:
			wrpll_params->pdiv = 2;
			break;
		 case 7:
			wrpll_params->pdiv = 4;
			break;
		 default:
			WARN(1, "Incorrect PDiv\n");
		 }

		 switch (candidate_p2[min_dco_index]) {
		 case 5:
			wrpll_params->kdiv = 0;
			break;
		 case 2:
			wrpll_params->kdiv = 1;
			break;
		 case 3:
			wrpll_params->kdiv = 2;
			break;
		 case 1:
			wrpll_params->kdiv = 3;
			break;
		 default:
			WARN(1, "Incorrect KDiv\n");
		 }

		 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
		 wrpll_params->qdiv_mode =
			(wrpll_params->qdiv_ratio == 1) ? 0 : 1;

		 dco_freq = candidate_p0[min_dco_index] *
			 candidate_p1[min_dco_index] *
			 candidate_p2[min_dco_index] * afe_clock;

		/*
		* Intermediate values are in Hz.
		* Divide by MHz to match bsepc
		*/
		 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
		 wrpll_params->dco_fraction =
			 div_u64(((div_u64(dco_freq, 24) -
				   wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));

	}
}


static bool
skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1133
		   struct intel_crtc_state *crtc_state,
1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182
		   struct intel_encoder *intel_encoder,
		   int clock)
{
	struct intel_shared_dpll *pll;
	uint32_t ctrl1, cfgcr1, cfgcr2;

	/*
	 * See comment in intel_dpll_hw_state to understand why we always use 0
	 * as the DPLL id in this function.
	 */

	ctrl1 = DPLL_CTRL1_OVERRIDE(0);

	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		struct skl_wrpll_params wrpll_params = { 0, };

		ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);

		skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);

		cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
			 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
			 wrpll_params.dco_integer;

		cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
			 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
			 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
			 wrpll_params.central_freq;
	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
		struct drm_encoder *encoder = &intel_encoder->base;
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

		switch (intel_dp->link_bw) {
		case DP_LINK_BW_1_62:
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
			break;
		case DP_LINK_BW_2_7:
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
			break;
		case DP_LINK_BW_5_4:
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
			break;
		}

		cfgcr1 = cfgcr2 = 0;
	} else /* eDP */
		return true;

1183 1184 1185
	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1186

1187
	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1188 1189 1190 1191 1192 1193 1194
	if (pll == NULL) {
		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
				 pipe_name(intel_crtc->pipe));
		return false;
	}

	/* shared DPLL id 0 is DPLL 1 */
1195
	crtc_state->ddi_pll_sel = pll->id + 1;
1196 1197 1198

	return true;
}
1199 1200 1201 1202 1203 1204 1205 1206

/*
 * Tries to find a *shared* PLL for the CRTC and store it in
 * intel_crtc->ddi_pll_sel.
 *
 * For private DPLLs, compute_config() should do the selection for us. This
 * function should be folded into compute_config() eventually.
 */
1207 1208
bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
			  struct intel_crtc_state *crtc_state)
1209
{
1210
	struct drm_device *dev = intel_crtc->base.dev;
1211 1212
	struct intel_encoder *intel_encoder =
		intel_ddi_get_crtc_new_encoder(intel_crtc);
1213
	int clock = crtc_state->port_clock;
1214

1215
	if (IS_SKYLAKE(dev))
1216 1217
		return skl_ddi_pll_select(intel_crtc, crtc_state,
					  intel_encoder, clock);
1218
	else
1219 1220
		return hsw_ddi_pll_select(intel_crtc, crtc_state,
					  intel_encoder, clock);
1221 1222
}

1223 1224 1225 1226 1227
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1228
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1229 1230 1231
	int type = intel_encoder->type;
	uint32_t temp;

1232
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1233
		temp = TRANS_MSA_SYNC_CLK;
1234
		switch (intel_crtc->config->pipe_bpp) {
1235
		case 18:
1236
			temp |= TRANS_MSA_6_BPC;
1237 1238
			break;
		case 24:
1239
			temp |= TRANS_MSA_8_BPC;
1240 1241
			break;
		case 30:
1242
			temp |= TRANS_MSA_10_BPC;
1243 1244
			break;
		case 36:
1245
			temp |= TRANS_MSA_12_BPC;
1246 1247
			break;
		default:
1248
			BUG();
1249
		}
1250
		I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1251 1252 1253
	}
}

1254 1255 1256 1257 1258
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1259
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1260 1261 1262 1263 1264 1265 1266 1267 1268
	uint32_t temp;
	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
	if (state == true)
		temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
	else
		temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}

1269
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1270 1271 1272
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1273
	struct drm_encoder *encoder = &intel_encoder->base;
1274 1275
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1276
	enum pipe pipe = intel_crtc->pipe;
1277
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1278
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1279
	int type = intel_encoder->type;
1280 1281
	uint32_t temp;

1282 1283
	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
	temp = TRANS_DDI_FUNC_ENABLE;
1284
	temp |= TRANS_DDI_SELECT_PORT(port);
1285

1286
	switch (intel_crtc->config->pipe_bpp) {
1287
	case 18:
1288
		temp |= TRANS_DDI_BPC_6;
1289 1290
		break;
	case 24:
1291
		temp |= TRANS_DDI_BPC_8;
1292 1293
		break;
	case 30:
1294
		temp |= TRANS_DDI_BPC_10;
1295 1296
		break;
	case 36:
1297
		temp |= TRANS_DDI_BPC_12;
1298 1299
		break;
	default:
1300
		BUG();
1301
	}
1302

1303
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1304
		temp |= TRANS_DDI_PVSYNC;
1305
	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1306
		temp |= TRANS_DDI_PHSYNC;
1307

1308 1309 1310
	if (cpu_transcoder == TRANSCODER_EDP) {
		switch (pipe) {
		case PIPE_A:
1311 1312 1313 1314
			/* On Haswell, can only use the always-on power well for
			 * eDP when not using the panel fitter, and when not
			 * using motion blur mitigation (which we don't
			 * support). */
1315
			if (IS_HASWELL(dev) &&
1316 1317
			    (intel_crtc->config->pch_pfit.enabled ||
			     intel_crtc->config->pch_pfit.force_thru))
1318 1319 1320
				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
			else
				temp |= TRANS_DDI_EDP_INPUT_A_ON;
1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
			break;
		case PIPE_B:
			temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
			break;
		case PIPE_C:
			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
			break;
		default:
			BUG();
			break;
		}
	}

1334
	if (type == INTEL_OUTPUT_HDMI) {
1335
		if (intel_crtc->config->has_hdmi_sink)
1336
			temp |= TRANS_DDI_MODE_SELECT_HDMI;
1337
		else
1338
			temp |= TRANS_DDI_MODE_SELECT_DVI;
1339

1340
	} else if (type == INTEL_OUTPUT_ANALOG) {
1341
		temp |= TRANS_DDI_MODE_SELECT_FDI;
1342
		temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1343 1344 1345 1346 1347

	} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
		   type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360
		if (intel_dp->is_mst) {
			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
		} else
			temp |= TRANS_DDI_MODE_SELECT_DP_SST;

		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
	} else if (type == INTEL_OUTPUT_DP_MST) {
		struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;

		if (intel_dp->is_mst) {
			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
		} else
			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1361

1362
		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1363
	} else {
1364 1365
		WARN(1, "Invalid encoder type %d for pipe %c\n",
		     intel_encoder->type, pipe_name(pipe));
1366 1367
	}

1368
	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1369
}
1370

1371 1372
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
				       enum transcoder cpu_transcoder)
1373
{
1374
	uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1375 1376
	uint32_t val = I915_READ(reg);

1377
	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1378
	val |= TRANS_DDI_PORT_NONE;
1379
	I915_WRITE(reg, val);
1380 1381
}

1382 1383 1384 1385 1386 1387 1388 1389 1390
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
{
	struct drm_device *dev = intel_connector->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	int type = intel_connector->base.connector_type;
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
	enum pipe pipe = 0;
	enum transcoder cpu_transcoder;
1391
	enum intel_display_power_domain power_domain;
1392 1393
	uint32_t tmp;

1394
	power_domain = intel_display_port_power_domain(intel_encoder);
1395
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
1396 1397
		return false;

1398 1399 1400 1401 1402 1403
	if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
		return false;

	if (port == PORT_A)
		cpu_transcoder = TRANSCODER_EDP;
	else
1404
		cpu_transcoder = (enum transcoder) pipe;
1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416

	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));

	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
	case TRANS_DDI_MODE_SELECT_HDMI:
	case TRANS_DDI_MODE_SELECT_DVI:
		return (type == DRM_MODE_CONNECTOR_HDMIA);

	case TRANS_DDI_MODE_SELECT_DP_SST:
		if (type == DRM_MODE_CONNECTOR_eDP)
			return true;
		return (type == DRM_MODE_CONNECTOR_DisplayPort);
1417 1418 1419 1420
	case TRANS_DDI_MODE_SELECT_DP_MST:
		/* if the transcoder is in MST state then
		 * connector isn't connected */
		return false;
1421 1422 1423 1424 1425 1426 1427 1428 1429

	case TRANS_DDI_MODE_SELECT_FDI:
		return (type == DRM_MODE_CONNECTOR_VGA);

	default:
		return false;
	}
}

1430 1431 1432 1433 1434
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
			    enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1435
	enum port port = intel_ddi_get_encoder_port(encoder);
1436
	enum intel_display_power_domain power_domain;
1437 1438 1439
	u32 tmp;
	int i;

1440
	power_domain = intel_display_port_power_domain(encoder);
1441
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
1442 1443
		return false;

1444
	tmp = I915_READ(DDI_BUF_CTL(port));
1445 1446 1447 1448

	if (!(tmp & DDI_BUF_CTL_ENABLE))
		return false;

1449 1450
	if (port == PORT_A) {
		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1451

1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		case TRANS_DDI_EDP_INPUT_A_ON:
		case TRANS_DDI_EDP_INPUT_A_ONOFF:
			*pipe = PIPE_A;
			break;
		case TRANS_DDI_EDP_INPUT_B_ONOFF:
			*pipe = PIPE_B;
			break;
		case TRANS_DDI_EDP_INPUT_C_ONOFF:
			*pipe = PIPE_C;
			break;
		}

		return true;
	} else {
		for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
			tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));

			if ((tmp & TRANS_DDI_PORT_MASK)
			    == TRANS_DDI_SELECT_PORT(port)) {
1472 1473 1474
				if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
					return false;

1475 1476 1477
				*pipe = i;
				return true;
			}
1478 1479 1480
		}
	}

1481
	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1482

1483
	return false;
1484 1485
}

1486 1487 1488 1489 1490 1491
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
{
	struct drm_crtc *crtc = &intel_crtc->base;
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1492
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1493

1494 1495 1496
	if (cpu_transcoder != TRANSCODER_EDP)
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
			   TRANS_CLK_SEL_PORT(port));
1497 1498 1499 1500 1501
}

void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1502
	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1503

1504 1505 1506
	if (cpu_transcoder != TRANSCODER_EDP)
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
			   TRANS_CLK_SEL_DISABLED);
1507 1508
}

1509
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1510
{
1511
	struct drm_encoder *encoder = &intel_encoder->base;
1512 1513
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1514
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1515
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1516
	int type = intel_encoder->type;
1517

1518 1519
	if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1520
		intel_edp_panel_on(intel_dp);
1521
	}
1522

1523
	if (IS_SKYLAKE(dev)) {
1524
		uint32_t dpll = crtc->config->ddi_pll_sel;
1525 1526
		uint32_t val;

1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538
		/*
		 * DPLL0 is used for eDP and is the only "private" DPLL (as
		 * opposed to shared) on SKL
		 */
		if (type == INTEL_OUTPUT_EDP) {
			WARN_ON(dpll != SKL_DPLL0);

			val = I915_READ(DPLL_CTRL1);

			val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
				 DPLL_CTRL1_SSC(dpll) |
				 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1539
			val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
1540 1541 1542 1543 1544 1545

			I915_WRITE(DPLL_CTRL1, val);
			POSTING_READ(DPLL_CTRL1);
		}

		/* DDI -> PLL mapping  */
1546 1547 1548 1549 1550 1551 1552 1553
		val = I915_READ(DPLL_CTRL2);

		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
			DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
		val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));

		I915_WRITE(DPLL_CTRL2, val);
1554

1555
	} else {
1556 1557
		WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
		I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
1558
	}
1559

1560
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1561
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1562

1563
		intel_ddi_init_dp_buf_reg(intel_encoder);
1564 1565 1566 1567

		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
1568
		if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
1569
			intel_dp_stop_link_train(intel_dp);
1570 1571 1572 1573
	} else if (type == INTEL_OUTPUT_HDMI) {
		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

		intel_hdmi->set_infoframes(encoder,
1574 1575
					   crtc->config->has_hdmi_sink,
					   &crtc->config->base.adjusted_mode);
1576
	}
1577 1578
}

1579
static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1580 1581
{
	struct drm_encoder *encoder = &intel_encoder->base;
1582 1583
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1584
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1585
	int type = intel_encoder->type;
1586
	uint32_t val;
1587
	bool wait = false;
1588 1589 1590 1591 1592

	val = I915_READ(DDI_BUF_CTL(port));
	if (val & DDI_BUF_CTL_ENABLE) {
		val &= ~DDI_BUF_CTL_ENABLE;
		I915_WRITE(DDI_BUF_CTL(port), val);
1593
		wait = true;
1594
	}
1595

1596 1597 1598 1599 1600 1601 1602 1603
	val = I915_READ(DP_TP_CTL(port));
	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
	I915_WRITE(DP_TP_CTL(port), val);

	if (wait)
		intel_wait_ddi_buf_idle(dev_priv, port);

1604
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1605
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1606
		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1607
		intel_edp_panel_vdd_on(intel_dp);
1608
		intel_edp_panel_off(intel_dp);
1609 1610
	}

1611 1612 1613 1614 1615
	if (IS_SKYLAKE(dev))
		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
					DPLL_CTRL2_DDI_CLK_OFF(port)));
	else
		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1616 1617
}

1618
static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1619
{
1620
	struct drm_encoder *encoder = &intel_encoder->base;
1621 1622
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1623
	struct drm_device *dev = encoder->dev;
1624
	struct drm_i915_private *dev_priv = dev->dev_private;
1625 1626
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
	int type = intel_encoder->type;
1627

1628
	if (type == INTEL_OUTPUT_HDMI) {
1629 1630 1631
		struct intel_digital_port *intel_dig_port =
			enc_to_dig_port(encoder);

1632 1633 1634 1635
		/* In HDMI/DVI mode, the port width, and swing/emphasis values
		 * are ignored so nothing special needs to be done besides
		 * enabling the port.
		 */
1636
		I915_WRITE(DDI_BUF_CTL(port),
1637 1638
			   intel_dig_port->saved_port_bits |
			   DDI_BUF_CTL_ENABLE);
1639 1640 1641
	} else if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

1642
		if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
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			intel_dp_stop_link_train(intel_dp);

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		intel_edp_backlight_on(intel_dp);
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1646
		intel_psr_enable(intel_dp);
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		intel_edp_drrs_enable(intel_dp);
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	}
1649

1650
	if (intel_crtc->config->has_audio) {
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		intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
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		intel_audio_codec_enable(intel_encoder);
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	}
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}

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static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1657
{
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	struct drm_encoder *encoder = &intel_encoder->base;
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	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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	int type = intel_encoder->type;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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1665
	if (intel_crtc->config->has_audio) {
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		intel_audio_codec_disable(intel_encoder);
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		intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
	}
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	if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

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1673
		intel_edp_drrs_disable(intel_dp);
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1674
		intel_psr_disable(intel_dp);
1675
		intel_edp_backlight_off(intel_dp);
1676
	}
1677
}
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static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
{
	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
	uint32_t cdctl = I915_READ(CDCLK_CTL);
	uint32_t linkrate;

	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
		WARN(1, "LCPLL1 not enabled\n");
		return 24000; /* 24MHz is the cd freq with NSSC ref */
	}

	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
		return 540000;

	linkrate = (I915_READ(DPLL_CTRL1) &
		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;

	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
		/* vco 8640 */
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
		case CDCLK_FREQ_450_432:
			return 432000;
		case CDCLK_FREQ_337_308:
			return 308570;
		case CDCLK_FREQ_675_617:
			return 617140;
		default:
			WARN(1, "Unknown cd freq selection\n");
		}
	} else {
		/* vco 8100 */
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
		case CDCLK_FREQ_450_432:
			return 450000;
		case CDCLK_FREQ_337_308:
			return 337500;
		case CDCLK_FREQ_675_617:
			return 675000;
		default:
			WARN(1, "Unknown cd freq selection\n");
		}
	}

	/* error case, do as if DPLL0 isn't enabled */
	return 24000;
}

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static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
{
	uint32_t lcpll = I915_READ(LCPLL_CTL);
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;

	if (lcpll & LCPLL_CD_SOURCE_FCLK)
		return 800000;
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
		return 450000;
	else if (freq == LCPLL_CLK_FREQ_450)
		return 450000;
	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
		return 540000;
	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
		return 337500;
	else
		return 675000;
}

static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1747
{
1748
	struct drm_device *dev = dev_priv->dev;
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	uint32_t lcpll = I915_READ(LCPLL_CTL);
1750
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
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1752
	if (lcpll & LCPLL_CD_SOURCE_FCLK)
1753
		return 800000;
1754
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1755
		return 450000;
1756
	else if (freq == LCPLL_CLK_FREQ_450)
1757
		return 450000;
1758
	else if (IS_HSW_ULT(dev))
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		return 337500;
	else
		return 540000;
}

int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;

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	if (IS_SKYLAKE(dev))
		return skl_get_cdclk_freq(dev_priv);

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	if (IS_BROADWELL(dev))
		return bdw_get_cdclk_freq(dev_priv);

	/* Haswell */
	return hsw_get_cdclk_freq(dev_priv);
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}

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static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
			       struct intel_shared_dpll *pll)
{
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	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
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	POSTING_READ(WRPLL_CTL(pll->id));
	udelay(20);
}

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static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
				struct intel_shared_dpll *pll)
{
	uint32_t val;

	val = I915_READ(WRPLL_CTL(pll->id));
	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
	POSTING_READ(WRPLL_CTL(pll->id));
}

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static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
				     struct intel_shared_dpll *pll,
				     struct intel_dpll_hw_state *hw_state)
{
	uint32_t val;

1802
	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
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		return false;

	val = I915_READ(WRPLL_CTL(pll->id));
	hw_state->wrpll = val;

	return val & WRPLL_PLL_ENABLE;
}

1811
static const char * const hsw_ddi_pll_names[] = {
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	"WRPLL 1",
	"WRPLL 2",
};

1816
static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1817
{
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	int i;

1820
	dev_priv->num_shared_dpll = 2;
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1822
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
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		dev_priv->shared_dplls[i].id = i;
		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1825
		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1826
		dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
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		dev_priv->shared_dplls[i].get_hw_state =
			hsw_ddi_pll_get_hw_state;
1829
	}
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}

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static const char * const skl_ddi_pll_names[] = {
	"DPLL 1",
	"DPLL 2",
	"DPLL 3",
};

struct skl_dpll_regs {
	u32 ctl, cfgcr1, cfgcr2;
};

/* this array is indexed by the *shared* pll id */
static const struct skl_dpll_regs skl_dpll_regs[3] = {
	{
		/* DPLL 1 */
		.ctl = LCPLL2_CTL,
		.cfgcr1 = DPLL1_CFGCR1,
		.cfgcr2 = DPLL1_CFGCR2,
	},
	{
		/* DPLL 2 */
		.ctl = WRPLL_CTL1,
		.cfgcr1 = DPLL2_CFGCR1,
		.cfgcr2 = DPLL2_CFGCR2,
	},
	{
		/* DPLL 3 */
		.ctl = WRPLL_CTL2,
		.cfgcr1 = DPLL3_CFGCR1,
		.cfgcr2 = DPLL3_CFGCR2,
	},
};

static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
			       struct intel_shared_dpll *pll)
{
	uint32_t val;
	unsigned int dpll;
	const struct skl_dpll_regs *regs = skl_dpll_regs;

	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
	dpll = pll->id + 1;

	val = I915_READ(DPLL_CTRL1);

	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
		 DPLL_CRTL1_LINK_RATE_MASK(dpll));
	val |= pll->config.hw_state.ctrl1 << (dpll * 6);

	I915_WRITE(DPLL_CTRL1, val);
	POSTING_READ(DPLL_CTRL1);

	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
	I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
	POSTING_READ(regs[pll->id].cfgcr1);
	POSTING_READ(regs[pll->id].cfgcr2);

	/* the enable bit is always bit 31 */
	I915_WRITE(regs[pll->id].ctl,
		   I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);

	if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
		DRM_ERROR("DPLL %d not locked\n", dpll);
}

static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
				struct intel_shared_dpll *pll)
{
	const struct skl_dpll_regs *regs = skl_dpll_regs;

	/* the enable bit is always bit 31 */
	I915_WRITE(regs[pll->id].ctl,
		   I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
	POSTING_READ(regs[pll->id].ctl);
}

static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
				     struct intel_shared_dpll *pll,
				     struct intel_dpll_hw_state *hw_state)
{
	uint32_t val;
	unsigned int dpll;
	const struct skl_dpll_regs *regs = skl_dpll_regs;

	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
		return false;

	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
	dpll = pll->id + 1;

	val = I915_READ(regs[pll->id].ctl);
	if (!(val & LCPLL_PLL_ENABLE))
		return false;

	val = I915_READ(DPLL_CTRL1);
	hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;

	/* avoid reading back stale values if HDMI mode is not enabled */
	if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
	}

	return true;
}

static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
{
	int i;

	dev_priv->num_shared_dpll = 3;

	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		dev_priv->shared_dplls[i].id = i;
		dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
		dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
		dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
		dev_priv->shared_dplls[i].get_hw_state =
			skl_ddi_pll_get_hw_state;
	}
}

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void intel_ddi_pll_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t val = I915_READ(LCPLL_CTL);

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	if (IS_SKYLAKE(dev))
		skl_shared_dplls_init(dev_priv);
	else
		hsw_shared_dplls_init(dev_priv);
1962

1963
	DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1964 1965
		      intel_ddi_get_cdclk_freq(dev_priv));

1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977
	if (IS_SKYLAKE(dev)) {
		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
			DRM_ERROR("LCPLL1 is disabled\n");
	} else {
		/*
		 * The LCPLL register should be turned on by the BIOS. For now
		 * let's just check its state and print errors in case
		 * something is wrong.  Don't even try to turn it on.
		 */

		if (val & LCPLL_CD_SOURCE_FCLK)
			DRM_ERROR("CDCLK source is not LCPLL\n");
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1979 1980 1981
		if (val & LCPLL_PLL_DISABLE)
			DRM_ERROR("LCPLL is disabled\n");
	}
1982
}
1983 1984 1985

void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
{
1986 1987
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
1988
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1989
	enum port port = intel_dig_port->port;
1990
	uint32_t val;
1991
	bool wait = false;
1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010

	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
		val = I915_READ(DDI_BUF_CTL(port));
		if (val & DDI_BUF_CTL_ENABLE) {
			val &= ~DDI_BUF_CTL_ENABLE;
			I915_WRITE(DDI_BUF_CTL(port), val);
			wait = true;
		}

		val = I915_READ(DP_TP_CTL(port));
		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
		I915_WRITE(DP_TP_CTL(port), val);
		POSTING_READ(DP_TP_CTL(port));

		if (wait)
			intel_wait_ddi_buf_idle(dev_priv, port);
	}

2011
	val = DP_TP_CTL_ENABLE |
2012
	      DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2013 2014 2015 2016 2017 2018 2019
	if (intel_dp->is_mst)
		val |= DP_TP_CTL_MODE_MST;
	else {
		val |= DP_TP_CTL_MODE_SST;
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
	}
2020 2021 2022 2023 2024 2025 2026 2027 2028
	I915_WRITE(DP_TP_CTL(port), val);
	POSTING_READ(DP_TP_CTL(port));

	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
	POSTING_READ(DDI_BUF_CTL(port));

	udelay(600);
}
2029

2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055
void intel_ddi_fdi_disable(struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
	uint32_t val;

	intel_ddi_post_disable(intel_encoder);

	val = I915_READ(_FDI_RXA_CTL);
	val &= ~FDI_RX_ENABLE;
	I915_WRITE(_FDI_RXA_CTL, val);

	val = I915_READ(_FDI_RXA_MISC);
	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
	I915_WRITE(_FDI_RXA_MISC, val);

	val = I915_READ(_FDI_RXA_CTL);
	val &= ~FDI_PCDCLK;
	I915_WRITE(_FDI_RXA_CTL, val);

	val = I915_READ(_FDI_RXA_CTL);
	val &= ~FDI_RX_PLL_ENABLE;
	I915_WRITE(_FDI_RXA_CTL, val);
}

2056 2057
static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
{
2058 2059 2060 2061 2062 2063 2064 2065
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
	int type = intel_dig_port->base.type;

	if (type != INTEL_OUTPUT_DISPLAYPORT &&
	    type != INTEL_OUTPUT_EDP &&
	    type != INTEL_OUTPUT_UNKNOWN) {
		return;
	}
2066

2067
	intel_dp_hot_plug(intel_encoder);
2068 2069
}

2070
void intel_ddi_get_config(struct intel_encoder *encoder,
2071
			  struct intel_crtc_state *pipe_config)
2072 2073 2074
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2075
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2076
	struct intel_hdmi *intel_hdmi;
2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088
	u32 temp, flags = 0;

	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
	if (temp & TRANS_DDI_PHSYNC)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (temp & TRANS_DDI_PVSYNC)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

2089
	pipe_config->base.adjusted_mode.flags |= flags;
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	switch (temp & TRANS_DDI_BPC_MASK) {
	case TRANS_DDI_BPC_6:
		pipe_config->pipe_bpp = 18;
		break;
	case TRANS_DDI_BPC_8:
		pipe_config->pipe_bpp = 24;
		break;
	case TRANS_DDI_BPC_10:
		pipe_config->pipe_bpp = 30;
		break;
	case TRANS_DDI_BPC_12:
		pipe_config->pipe_bpp = 36;
		break;
	default:
		break;
	}
2107 2108 2109

	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
	case TRANS_DDI_MODE_SELECT_HDMI:
2110
		pipe_config->has_hdmi_sink = true;
2111 2112 2113 2114
		intel_hdmi = enc_to_intel_hdmi(&encoder->base);

		if (intel_hdmi->infoframe_enabled(&encoder->base))
			pipe_config->has_infoframe = true;
2115
		break;
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	case TRANS_DDI_MODE_SELECT_DVI:
	case TRANS_DDI_MODE_SELECT_FDI:
		break;
	case TRANS_DDI_MODE_SELECT_DP_SST:
	case TRANS_DDI_MODE_SELECT_DP_MST:
		pipe_config->has_dp_encoder = true;
		intel_dp_get_m_n(intel_crtc, pipe_config);
		break;
	default:
		break;
	}
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2128
	if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2129
		temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2130
		if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2131 2132
			pipe_config->has_audio = true;
	}
2133

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	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
2153

2154
	intel_ddi_clock_get(encoder, pipe_config);
2155 2156
}

2157 2158 2159 2160 2161 2162
static void intel_ddi_destroy(struct drm_encoder *encoder)
{
	/* HDMI has nothing special to destroy, so we can go with this. */
	intel_dp_encoder_destroy(encoder);
}

2163
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2164
				     struct intel_crtc_state *pipe_config)
2165
{
2166
	int type = encoder->type;
2167
	int port = intel_ddi_get_encoder_port(encoder);
2168

2169
	WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2170

2171 2172 2173
	if (port == PORT_A)
		pipe_config->cpu_transcoder = TRANSCODER_EDP;

2174
	if (type == INTEL_OUTPUT_HDMI)
2175
		return intel_hdmi_compute_config(encoder, pipe_config);
2176
	else
2177
		return intel_dp_compute_config(encoder, pipe_config);
2178 2179 2180 2181 2182 2183
}

static const struct drm_encoder_funcs intel_ddi_funcs = {
	.destroy = intel_ddi_destroy,
};

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static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
{
	struct intel_connector *connector;
	enum port port = intel_dig_port->port;

	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
	if (!connector)
		return NULL;

	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
	if (!intel_dp_init_connector(intel_dig_port, connector)) {
		kfree(connector);
		return NULL;
	}

	return connector;
}

static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
{
	struct intel_connector *connector;
	enum port port = intel_dig_port->port;

	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
	if (!connector)
		return NULL;

	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
	intel_hdmi_init_connector(intel_dig_port, connector);

	return connector;
}

2219 2220
void intel_ddi_init(struct drm_device *dev, enum port port)
{
2221
	struct drm_i915_private *dev_priv = dev->dev_private;
2222 2223 2224
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
2225 2226 2227 2228 2229 2230
	bool init_hdmi, init_dp;

	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
	if (!init_dp && !init_hdmi) {
2231
		DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2232 2233 2234 2235
			      port_name(port));
		init_hdmi = true;
		init_dp = true;
	}
2236

2237
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2238 2239 2240 2241 2242 2243 2244 2245 2246
	if (!intel_dig_port)
		return;

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, encoder, &intel_ddi_funcs,
			 DRM_MODE_ENCODER_TMDS);

2247
	intel_encoder->compute_config = intel_ddi_compute_config;
2248 2249 2250 2251 2252
	intel_encoder->enable = intel_enable_ddi;
	intel_encoder->pre_enable = intel_ddi_pre_enable;
	intel_encoder->disable = intel_disable_ddi;
	intel_encoder->post_disable = intel_ddi_post_disable;
	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2253
	intel_encoder->get_config = intel_ddi_get_config;
2254 2255

	intel_dig_port->port = port;
2256 2257 2258
	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
					  (DDI_BUF_PORT_REVERSAL |
					   DDI_A_4_LANES);
2259 2260

	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2261
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2262
	intel_encoder->cloneable = 0;
2263 2264
	intel_encoder->hot_plug = intel_ddi_hot_plug;

2265 2266 2267
	if (init_dp) {
		if (!intel_ddi_init_dp_connector(intel_dig_port))
			goto err;
2268

2269 2270 2271
		intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
		dev_priv->hpd_irq_port[port] = intel_dig_port;
	}
2272

2273 2274
	/* In theory we don't need the encoder->type check, but leave it just in
	 * case we have some really bad VBTs... */
2275 2276 2277
	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
		if (!intel_ddi_init_hdmi_connector(intel_dig_port))
			goto err;
2278
	}
2279 2280 2281 2282 2283 2284

	return;

err:
	drm_encoder_cleanup(encoder);
	kfree(intel_dig_port);
2285
}