intel_ddi.c 59.7 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eugeni Dodonov <eugeni.dodonov@intel.com>
 *
 */

#include "i915_drv.h"
#include "intel_drv.h"

31 32 33 34 35
struct ddi_buf_trans {
	u32 trans1;	/* balance leg enable, de-emph level */
	u32 trans2;	/* vref sel, vswing */
};

36 37 38 39
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
 * them for both DP and FDI transports, allowing those ports to
 * automatically adapt to HDMI connections as well
 */
40 41 42 43 44 45 46 47 48 49
static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
	{ 0x00FFFFFF, 0x0006000E },
	{ 0x00D75FFF, 0x0005000A },
	{ 0x00C30FFF, 0x00040006 },
	{ 0x80AAAFFF, 0x000B0000 },
	{ 0x00FFFFFF, 0x0005000A },
	{ 0x00D75FFF, 0x000C0004 },
	{ 0x80C30FFF, 0x000B0000 },
	{ 0x00FFFFFF, 0x00040006 },
	{ 0x80D75FFF, 0x000B0000 },
50 51
};

52 53 54 55 56 57 58 59 60 61
static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
	{ 0x00FFFFFF, 0x0007000E },
	{ 0x00D75FFF, 0x000F000A },
	{ 0x00C30FFF, 0x00060006 },
	{ 0x00AAAFFF, 0x001E0000 },
	{ 0x00FFFFFF, 0x000F000A },
	{ 0x00D75FFF, 0x00160004 },
	{ 0x00C30FFF, 0x001E0000 },
	{ 0x00FFFFFF, 0x00060006 },
	{ 0x00D75FFF, 0x001E0000 },
62 63
};

64 65 66 67 68 69 70 71 72 73 74 75 76 77
static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
					/* Idx	NT mV d	T mV d	db	*/
	{ 0x00FFFFFF, 0x0006000E },	/* 0:	400	400	0	*/
	{ 0x00E79FFF, 0x000E000C },	/* 1:	400	500	2	*/
	{ 0x00D75FFF, 0x0005000A },	/* 2:	400	600	3.5	*/
	{ 0x00FFFFFF, 0x0005000A },	/* 3:	600	600	0	*/
	{ 0x00E79FFF, 0x001D0007 },	/* 4:	600	750	2	*/
	{ 0x00D75FFF, 0x000C0004 },	/* 5:	600	900	3.5	*/
	{ 0x00FFFFFF, 0x00040006 },	/* 6:	800	800	0	*/
	{ 0x80E79FFF, 0x00030002 },	/* 7:	800	1000	2	*/
	{ 0x00FFFFFF, 0x00140005 },	/* 8:	850	850	0	*/
	{ 0x00FFFFFF, 0x000C0004 },	/* 9:	900	900	0	*/
	{ 0x00FFFFFF, 0x001C0003 },	/* 10:	950	950	0	*/
	{ 0x80FFFFFF, 0x00030002 },	/* 11:	1000	1000	0	*/
78 79
};

80 81 82 83 84 85 86 87 88 89
static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
	{ 0x00FFFFFF, 0x00000012 },
	{ 0x00EBAFFF, 0x00020011 },
	{ 0x00C71FFF, 0x0006000F },
	{ 0x00AAAFFF, 0x000E000A },
	{ 0x00FFFFFF, 0x00020011 },
	{ 0x00DB6FFF, 0x0005000F },
	{ 0x00BEEFFF, 0x000A000C },
	{ 0x00FFFFFF, 0x0005000F },
	{ 0x00DB6FFF, 0x000A000C },
90 91
};

92 93 94 95 96 97
static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
	{ 0x00FFFFFF, 0x0007000E },
	{ 0x00D75FFF, 0x000E000A },
	{ 0x00BEFFFF, 0x00140006 },
	{ 0x80B2CFFF, 0x001B0002 },
	{ 0x00FFFFFF, 0x000E000A },
98
	{ 0x00DB6FFF, 0x00160005 },
99
	{ 0x80C71FFF, 0x001A0002 },
100 101
	{ 0x00F7DFFF, 0x00180004 },
	{ 0x80D75FFF, 0x001B0002 },
102 103
};

104 105 106 107 108 109 110 111 112 113
static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
	{ 0x00FFFFFF, 0x0001000E },
	{ 0x00D75FFF, 0x0004000A },
	{ 0x00C30FFF, 0x00070006 },
	{ 0x00AAAFFF, 0x000C0000 },
	{ 0x00FFFFFF, 0x0004000A },
	{ 0x00D75FFF, 0x00090004 },
	{ 0x00C30FFF, 0x000C0000 },
	{ 0x00FFFFFF, 0x00070006 },
	{ 0x00D75FFF, 0x000C0000 },
114 115
};

116 117 118 119 120 121 122 123 124 125 126 127
static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
					/* Idx	NT mV d	T mV df	db	*/
	{ 0x00FFFFFF, 0x0007000E },	/* 0:	400	400	0	*/
	{ 0x00D75FFF, 0x000E000A },	/* 1:	400	600	3.5	*/
	{ 0x00BEFFFF, 0x00140006 },	/* 2:	400	800	6	*/
	{ 0x00FFFFFF, 0x0009000D },	/* 3:	450	450	0	*/
	{ 0x00FFFFFF, 0x000E000A },	/* 4:	600	600	0	*/
	{ 0x00D7FFFF, 0x00140006 },	/* 5:	600	800	2.5	*/
	{ 0x80CB2FFF, 0x001B0002 },	/* 6:	600	1000	4.5	*/
	{ 0x00FFFFFF, 0x00140006 },	/* 7:	800	800	0	*/
	{ 0x80E79FFF, 0x001B0002 },	/* 8:	800	1000	2	*/
	{ 0x80FFFFFF, 0x001B0002 },	/* 9:	1000	1000	0	*/
128 129
};

130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155
static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
	{ 0x00000018, 0x000000a0 },
	{ 0x00004014, 0x00000098 },
	{ 0x00006012, 0x00000088 },
	{ 0x00008010, 0x00000080 },
	{ 0x00000018, 0x00000098 },
	{ 0x00004014, 0x00000088 },
	{ 0x00006012, 0x00000080 },
	{ 0x00000018, 0x00000088 },
	{ 0x00004014, 0x00000080 },
};

static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
					/* Idx	NT mV   T mV    db  */
	{ 0x00000018, 0x000000a0 },	/* 0:	400	400	0   */
	{ 0x00004014, 0x00000098 },	/* 1:	400	600	3.5 */
	{ 0x00006012, 0x00000088 },	/* 2:	400	800	6   */
	{ 0x00000018, 0x0000003c },	/* 3:	450	450	0   */
	{ 0x00000018, 0x00000098 },	/* 4:	600	600	0   */
	{ 0x00003015, 0x00000088 },	/* 5:	600	800	2.5 */
	{ 0x00005013, 0x00000080 },	/* 6:	600	1000	4.5 */
	{ 0x00000018, 0x00000088 },	/* 7:	800	800	0   */
	{ 0x00000096, 0x00000080 },	/* 8:	800	1000	2   */
	{ 0x00000018, 0x00000080 },	/* 9:	1200	1200	0   */
};

156
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
157
{
158
	struct drm_encoder *encoder = &intel_encoder->base;
159 160
	int type = intel_encoder->type;

161 162 163 164
	if (type == INTEL_OUTPUT_DP_MST) {
		struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
		return intel_dig_port->port;
	} else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
165
	    type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
166 167 168
		struct intel_digital_port *intel_dig_port =
			enc_to_dig_port(encoder);
		return intel_dig_port->port;
169

170 171
	} else if (type == INTEL_OUTPUT_ANALOG) {
		return PORT_E;
172

173 174 175 176 177 178
	} else {
		DRM_ERROR("Invalid DDI encoder type %d\n", type);
		BUG();
	}
}

179 180 181
/*
 * Starting with Haswell, DDI port buffers must be programmed with correct
 * values in advance. The buffer values are different for FDI and DP modes,
182 183 184 185
 * but the HDMI/DVI fields are shared among those. So we program the DDI
 * in either FDI or DP modes only, as HDMI connections will work with both
 * of those
 */
186
static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
187 188 189
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg;
190
	int i, n_hdmi_entries, hdmi_800mV_0dB;
191
	int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
192 193 194 195 196
	const struct ddi_buf_trans *ddi_translations_fdi;
	const struct ddi_buf_trans *ddi_translations_dp;
	const struct ddi_buf_trans *ddi_translations_edp;
	const struct ddi_buf_trans *ddi_translations_hdmi;
	const struct ddi_buf_trans *ddi_translations;
197

198 199 200 201 202 203 204 205
	if (IS_SKYLAKE(dev)) {
		ddi_translations_fdi = NULL;
		ddi_translations_dp = skl_ddi_translations_dp;
		ddi_translations_edp = skl_ddi_translations_dp;
		ddi_translations_hdmi = skl_ddi_translations_hdmi;
		n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
		hdmi_800mV_0dB = 7;
	} else if (IS_BROADWELL(dev)) {
206 207
		ddi_translations_fdi = bdw_ddi_translations_fdi;
		ddi_translations_dp = bdw_ddi_translations_dp;
208
		ddi_translations_edp = bdw_ddi_translations_edp;
209
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
210
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
211
		hdmi_800mV_0dB = 7;
212 213 214
	} else if (IS_HASWELL(dev)) {
		ddi_translations_fdi = hsw_ddi_translations_fdi;
		ddi_translations_dp = hsw_ddi_translations_dp;
215
		ddi_translations_edp = hsw_ddi_translations_dp;
216
		ddi_translations_hdmi = hsw_ddi_translations_hdmi;
217
		n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
218
		hdmi_800mV_0dB = 6;
219 220
	} else {
		WARN(1, "ddi translation table missing\n");
221
		ddi_translations_edp = bdw_ddi_translations_dp;
222 223
		ddi_translations_fdi = bdw_ddi_translations_fdi;
		ddi_translations_dp = bdw_ddi_translations_dp;
224
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
225
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
226
		hdmi_800mV_0dB = 7;
227 228
	}

229 230 231 232 233 234 235 236
	switch (port) {
	case PORT_A:
		ddi_translations = ddi_translations_edp;
		break;
	case PORT_B:
	case PORT_C:
		ddi_translations = ddi_translations_dp;
		break;
237
	case PORT_D:
238
		if (intel_dp_is_edp(dev, PORT_D))
239 240 241 242
			ddi_translations = ddi_translations_edp;
		else
			ddi_translations = ddi_translations_dp;
		break;
243
	case PORT_E:
244 245 246 247
		if (ddi_translations_fdi)
			ddi_translations = ddi_translations_fdi;
		else
			ddi_translations = ddi_translations_dp;
248 249 250 251
		break;
	default:
		BUG();
	}
252

253 254
	for (i = 0, reg = DDI_BUF_TRANS(port);
	     i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
255 256 257
		I915_WRITE(reg, ddi_translations[i].trans1);
		reg += 4;
		I915_WRITE(reg, ddi_translations[i].trans2);
258 259
		reg += 4;
	}
260 261 262 263 264 265

	/* Choose a good default if VBT is badly populated */
	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
	    hdmi_level >= n_hdmi_entries)
		hdmi_level = hdmi_800mV_0dB;

266
	/* Entry 9 is for HDMI: */
267 268 269 270
	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
	reg += 4;
	I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
	reg += 4;
271 272 273 274 275 276 277 278 279
}

/* Program DDI buffers translations for DP. By default, program ports A-D in DP
 * mode and port E for FDI.
 */
void intel_prepare_ddi(struct drm_device *dev)
{
	int port;

280 281
	if (!HAS_DDI(dev))
		return;
282

283 284
	for (port = PORT_A; port <= PORT_E; port++)
		intel_prepare_ddi_buffers(dev, port);
285
}
286

287 288 289 290 291 292 293 294 295 296 297 298 299
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
				    enum port port)
{
	uint32_t reg = DDI_BUF_CTL(port);
	int i;

	for (i = 0; i < 8; i++) {
		udelay(1);
		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
			return;
	}
	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
}
300 301 302 303 304 305 306 307 308 309 310 311 312 313 314

/* Starting with Haswell, different DDI ports can work in FDI mode for
 * connection to the PCH-located connectors. For this, it is necessary to train
 * both the DDI port and PCH receiver for the desired DDI buffer settings.
 *
 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 * please note that when FDI mode is active on DDI E, it shares 2 lines with
 * DDI A (which is used for eDP)
 */

void hsw_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
315
	u32 temp, i, rx_ctl_val;
316

317 318 319 320
	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
	 * mode set "sequence for CRT port" document:
	 * - TP1 to TP2 time with the default value
	 * - FDI delay to 90h
321 322
	 *
	 * WaFDIAutoLinkSetTimingOverrride:hsw
323 324 325 326 327 328
	 */
	I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
				  FDI_RX_PWRDN_LANE0_VAL(2) |
				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

	/* Enable the PCH Receiver FDI PLL */
329
	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
330
		     FDI_RX_PLL_ENABLE |
331
		     FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
332 333 334 335 336 337 338 339 340
	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
	POSTING_READ(_FDI_RXA_CTL);
	udelay(220);

	/* Switch from Rawclk to PCDclk */
	rx_ctl_val |= FDI_PCDCLK;
	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);

	/* Configure Port Clock Select */
341 342
	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
	WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
343 344 345

	/* Start the training iterating through available voltages and emphasis,
	 * testing each value twice. */
346
	for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
347 348 349 350 351 352 353
		/* Configure DP_TP_CTL with auto-training */
		I915_WRITE(DP_TP_CTL(PORT_E),
					DP_TP_CTL_FDI_AUTOTRAIN |
					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
					DP_TP_CTL_LINK_TRAIN_PAT1 |
					DP_TP_CTL_ENABLE);

354 355 356 357
		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
		 * DDI E does not support port reversal, the functionality is
		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
		 * port reversal bit */
358
		I915_WRITE(DDI_BUF_CTL(PORT_E),
359
			   DDI_BUF_CTL_ENABLE |
360
			   ((intel_crtc->config.fdi_lanes - 1) << 1) |
361
			   DDI_BUF_TRANS_SELECT(i / 2));
362
		POSTING_READ(DDI_BUF_CTL(PORT_E));
363 364 365

		udelay(600);

366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384
		/* Program PCH FDI Receiver TU */
		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));

		/* Enable PCH FDI Receiver with auto-training */
		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
		POSTING_READ(_FDI_RXA_CTL);

		/* Wait for FDI receiver lane calibration */
		udelay(30);

		/* Unset FDI_RX_MISC pwrdn lanes */
		temp = I915_READ(_FDI_RXA_MISC);
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
		I915_WRITE(_FDI_RXA_MISC, temp);
		POSTING_READ(_FDI_RXA_MISC);

		/* Wait for FDI auto training time */
		udelay(5);
385 386 387

		temp = I915_READ(DP_TP_STATUS(PORT_E));
		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
388
			DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
389 390 391

			/* Enable normal pixel sending for FDI */
			I915_WRITE(DP_TP_CTL(PORT_E),
392 393 394 395
				   DP_TP_CTL_FDI_AUTOTRAIN |
				   DP_TP_CTL_LINK_TRAIN_NORMAL |
				   DP_TP_CTL_ENHANCED_FRAME_ENABLE |
				   DP_TP_CTL_ENABLE);
396

397
			return;
398
		}
399

400 401 402 403 404
		temp = I915_READ(DDI_BUF_CTL(PORT_E));
		temp &= ~DDI_BUF_CTL_ENABLE;
		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
		POSTING_READ(DDI_BUF_CTL(PORT_E));

405
		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
406 407 408 409 410 411 412
		temp = I915_READ(DP_TP_CTL(PORT_E));
		temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
		I915_WRITE(DP_TP_CTL(PORT_E), temp);
		POSTING_READ(DP_TP_CTL(PORT_E));

		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
413 414 415

		rx_ctl_val &= ~FDI_RX_ENABLE;
		I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
416
		POSTING_READ(_FDI_RXA_CTL);
417 418 419 420 421 422

		/* Reset FDI_RX_MISC pwrdn lanes */
		temp = I915_READ(_FDI_RXA_MISC);
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
		I915_WRITE(_FDI_RXA_MISC, temp);
423
		POSTING_READ(_FDI_RXA_MISC);
424 425
	}

426
	DRM_ERROR("FDI link training failed!\n");
427
}
428

429 430 431 432 433 434 435
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);

	intel_dp->DP = intel_dig_port->saved_port_bits |
436
		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
437 438 439 440
	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);

}

441 442 443 444 445 446 447 448 449 450 451 452 453 454
static struct intel_encoder *
intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *intel_encoder, *ret = NULL;
	int num_encoders = 0;

	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		ret = intel_encoder;
		num_encoders++;
	}

	if (num_encoders != 1)
455 456
		WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
		     pipe_name(intel_crtc->pipe));
457 458 459 460 461

	BUG_ON(ret == NULL);
	return ret;
}

462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482
static struct intel_encoder *
intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct intel_encoder *intel_encoder, *ret = NULL;
	int num_encoders = 0;

	for_each_intel_encoder(dev, intel_encoder) {
		if (intel_encoder->new_crtc == crtc) {
			ret = intel_encoder;
			num_encoders++;
		}
	}

	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
	     pipe_name(crtc->pipe));

	BUG_ON(ret == NULL);
	return ret;
}

483
#define LC_FREQ 2700
484
#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
485 486 487 488 489 490 491 492 493 494 495

#define P_MIN 2
#define P_MAX 64
#define P_INC 2

/* Constraints for PLL good behavior */
#define REF_MIN 48
#define REF_MAX 400
#define VCO_MIN 2400
#define VCO_MAX 4800

496 497 498 499 500
#define abs_diff(a, b) ({			\
	typeof(a) __a = (a);			\
	typeof(b) __b = (b);			\
	(void) (&__a == &__b);			\
	__a > __b ? (__a - __b) : (__b - __a); })
501 502 503 504 505 506

struct wrpll_rnp {
	unsigned p, n2, r2;
};

static unsigned wrpll_get_budget_for_freq(int clock)
507
{
508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575
	unsigned budget;

	switch (clock) {
	case 25175000:
	case 25200000:
	case 27000000:
	case 27027000:
	case 37762500:
	case 37800000:
	case 40500000:
	case 40541000:
	case 54000000:
	case 54054000:
	case 59341000:
	case 59400000:
	case 72000000:
	case 74176000:
	case 74250000:
	case 81000000:
	case 81081000:
	case 89012000:
	case 89100000:
	case 108000000:
	case 108108000:
	case 111264000:
	case 111375000:
	case 148352000:
	case 148500000:
	case 162000000:
	case 162162000:
	case 222525000:
	case 222750000:
	case 296703000:
	case 297000000:
		budget = 0;
		break;
	case 233500000:
	case 245250000:
	case 247750000:
	case 253250000:
	case 298000000:
		budget = 1500;
		break;
	case 169128000:
	case 169500000:
	case 179500000:
	case 202000000:
		budget = 2000;
		break;
	case 256250000:
	case 262500000:
	case 270000000:
	case 272500000:
	case 273750000:
	case 280750000:
	case 281250000:
	case 286000000:
	case 291750000:
		budget = 4000;
		break;
	case 267250000:
	case 268500000:
		budget = 5000;
		break;
	default:
		budget = 1000;
		break;
	}
576

577 578 579 580 581 582 583 584
	return budget;
}

static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
			     unsigned r2, unsigned n2, unsigned p,
			     struct wrpll_rnp *best)
{
	uint64_t a, b, c, d, diff, diff_best;
585

586 587 588 589 590 591 592
	/* No best (r,n,p) yet */
	if (best->p == 0) {
		best->p = p;
		best->n2 = n2;
		best->r2 = r2;
		return;
	}
593

594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609
	/*
	 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
	 * freq2k.
	 *
	 * delta = 1e6 *
	 *	   abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
	 *	   freq2k;
	 *
	 * and we would like delta <= budget.
	 *
	 * If the discrepancy is above the PPM-based budget, always prefer to
	 * improve upon the previous solution.  However, if you're within the
	 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
	 */
	a = freq2k * budget * p * r2;
	b = freq2k * budget * best->p * best->r2;
610 611 612
	diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
	diff_best = abs_diff(freq2k * best->p * best->r2,
			     LC_FREQ_2K * best->n2);
613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638
	c = 1000000 * diff;
	d = 1000000 * diff_best;

	if (a < c && b < d) {
		/* If both are above the budget, pick the closer */
		if (best->p * best->r2 * diff < p * r2 * diff_best) {
			best->p = p;
			best->n2 = n2;
			best->r2 = r2;
		}
	} else if (a >= c && b < d) {
		/* If A is below the threshold but B is above it?  Update. */
		best->p = p;
		best->n2 = n2;
		best->r2 = r2;
	} else if (a >= c && b >= d) {
		/* Both are below the limit, so pick the higher n2/(r2*r2) */
		if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
			best->p = p;
			best->n2 = n2;
			best->r2 = r2;
		}
	}
	/* Otherwise a < c && b >= d, do nothing */
}

639 640 641 642 643 644 645 646
static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
				     int reg)
{
	int refclk = LC_FREQ;
	int n, p, r;
	u32 wrpll;

	wrpll = I915_READ(reg);
647 648 649
	switch (wrpll & WRPLL_PLL_REF_MASK) {
	case WRPLL_PLL_SSC:
	case WRPLL_PLL_NON_SSC:
650 651 652 653 654 655 656
		/*
		 * We could calculate spread here, but our checking
		 * code only cares about 5% accuracy, and spread is a max of
		 * 0.5% downspread.
		 */
		refclk = 135;
		break;
657
	case WRPLL_PLL_LCPLL:
658 659 660 661 662 663 664 665 666 667 668
		refclk = LC_FREQ;
		break;
	default:
		WARN(1, "bad wrpll refclk\n");
		return 0;
	}

	r = wrpll & WRPLL_DIVIDER_REF_MASK;
	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;

669 670
	/* Convert to KHz, p & r have a fixed point portion */
	return (refclk * n * 100) / (p * r);
671 672
}

673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781
static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
			       uint32_t dpll)
{
	uint32_t cfgcr1_reg, cfgcr2_reg;
	uint32_t cfgcr1_val, cfgcr2_val;
	uint32_t p0, p1, p2, dco_freq;

	cfgcr1_reg = GET_CFG_CR1_REG(dpll);
	cfgcr2_reg = GET_CFG_CR2_REG(dpll);

	cfgcr1_val = I915_READ(cfgcr1_reg);
	cfgcr2_val = I915_READ(cfgcr2_reg);

	p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
	p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;

	if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
		p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
	else
		p1 = 1;


	switch (p0) {
	case DPLL_CFGCR2_PDIV_1:
		p0 = 1;
		break;
	case DPLL_CFGCR2_PDIV_2:
		p0 = 2;
		break;
	case DPLL_CFGCR2_PDIV_3:
		p0 = 3;
		break;
	case DPLL_CFGCR2_PDIV_7:
		p0 = 7;
		break;
	}

	switch (p2) {
	case DPLL_CFGCR2_KDIV_5:
		p2 = 5;
		break;
	case DPLL_CFGCR2_KDIV_2:
		p2 = 2;
		break;
	case DPLL_CFGCR2_KDIV_3:
		p2 = 3;
		break;
	case DPLL_CFGCR2_KDIV_1:
		p2 = 1;
		break;
	}

	dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;

	dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
		1000) / 0x8000;

	return dco_freq / (p0 * p1 * p2 * 5);
}


static void skl_ddi_clock_get(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	enum port port = intel_ddi_get_encoder_port(encoder);
	int link_clock = 0;
	uint32_t dpll_ctl1, dpll;

	/* FIXME: This should be tracked in the pipe config. */
	dpll = I915_READ(DPLL_CTRL2);
	dpll &= DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
	dpll >>= DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);

	dpll_ctl1 = I915_READ(DPLL_CTRL1);

	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
		link_clock = skl_calc_wrpll_link(dev_priv, dpll);
	} else {
		link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
		link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);

		switch (link_clock) {
		case DPLL_CRTL1_LINK_RATE_810:
			link_clock = 81000;
			break;
		case DPLL_CRTL1_LINK_RATE_1350:
			link_clock = 135000;
			break;
		case DPLL_CRTL1_LINK_RATE_2700:
			link_clock = 270000;
			break;
		default:
			WARN(1, "Unsupported link rate\n");
			break;
		}
		link_clock *= 2;
	}

	pipe_config->port_clock = link_clock;

	if (pipe_config->has_dp_encoder)
		pipe_config->adjusted_mode.crtc_clock =
			intel_dotclock_calculate(pipe_config->port_clock,
						 &pipe_config->dp_m_n);
	else
		pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
}

782 783
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
			      struct intel_crtc_config *pipe_config)
784 785 786 787 788
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	int link_clock = 0;
	u32 val, pll;

789
	val = pipe_config->ddi_pll_sel;
790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837
	switch (val & PORT_CLK_SEL_MASK) {
	case PORT_CLK_SEL_LCPLL_810:
		link_clock = 81000;
		break;
	case PORT_CLK_SEL_LCPLL_1350:
		link_clock = 135000;
		break;
	case PORT_CLK_SEL_LCPLL_2700:
		link_clock = 270000;
		break;
	case PORT_CLK_SEL_WRPLL1:
		link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
		break;
	case PORT_CLK_SEL_WRPLL2:
		link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
		break;
	case PORT_CLK_SEL_SPLL:
		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
		if (pll == SPLL_PLL_FREQ_810MHz)
			link_clock = 81000;
		else if (pll == SPLL_PLL_FREQ_1350MHz)
			link_clock = 135000;
		else if (pll == SPLL_PLL_FREQ_2700MHz)
			link_clock = 270000;
		else {
			WARN(1, "bad spll freq\n");
			return;
		}
		break;
	default:
		WARN(1, "bad port clock sel\n");
		return;
	}

	pipe_config->port_clock = link_clock * 2;

	if (pipe_config->has_pch_encoder)
		pipe_config->adjusted_mode.crtc_clock =
			intel_dotclock_calculate(pipe_config->port_clock,
						 &pipe_config->fdi_m_n);
	else if (pipe_config->has_dp_encoder)
		pipe_config->adjusted_mode.crtc_clock =
			intel_dotclock_calculate(pipe_config->port_clock,
						 &pipe_config->dp_m_n);
	else
		pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
}

838 839 840 841 842 843
void intel_ddi_clock_get(struct intel_encoder *encoder,
			 struct intel_crtc_config *pipe_config)
{
	hsw_ddi_clock_get(encoder, pipe_config);
}

844
static void
845 846
hsw_ddi_calculate_wrpll(int clock /* in Hz */,
			unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902
{
	uint64_t freq2k;
	unsigned p, n2, r2;
	struct wrpll_rnp best = { 0, 0, 0 };
	unsigned budget;

	freq2k = clock / 100;

	budget = wrpll_get_budget_for_freq(clock);

	/* Special case handling for 540 pixel clock: bypass WR PLL entirely
	 * and directly pass the LC PLL to it. */
	if (freq2k == 5400000) {
		*n2_out = 2;
		*p_out = 1;
		*r2_out = 2;
		return;
	}

	/*
	 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
	 * the WR PLL.
	 *
	 * We want R so that REF_MIN <= Ref <= REF_MAX.
	 * Injecting R2 = 2 * R gives:
	 *   REF_MAX * r2 > LC_FREQ * 2 and
	 *   REF_MIN * r2 < LC_FREQ * 2
	 *
	 * Which means the desired boundaries for r2 are:
	 *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
	 *
	 */
	for (r2 = LC_FREQ * 2 / REF_MAX + 1;
	     r2 <= LC_FREQ * 2 / REF_MIN;
	     r2++) {

		/*
		 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
		 *
		 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
		 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
		 *   VCO_MAX * r2 > n2 * LC_FREQ and
		 *   VCO_MIN * r2 < n2 * LC_FREQ)
		 *
		 * Which means the desired boundaries for n2 are:
		 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
		 */
		for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
		     n2 <= VCO_MAX * r2 / LC_FREQ;
		     n2++) {

			for (p = P_MIN; p <= P_MAX; p += P_INC)
				wrpll_update_rnp(freq2k, budget,
						 r2, n2, p, &best);
		}
	}
903

904 905 906
	*n2_out = best.n2;
	*p_out = best.p;
	*r2_out = best.r2;
907 908
}

909
static bool
910 911 912
hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
		   struct intel_encoder *intel_encoder,
		   int clock)
913
{
914
	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
915
		struct intel_shared_dpll *pll;
916
		uint32_t val;
917
		unsigned p, n2, r2;
918

919
		hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
920

921
		val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
922 923 924
		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
		      WRPLL_DIVIDER_POST(p);

925
		intel_crtc->new_config->dpll_hw_state.wrpll = val;
926

927 928 929 930 931
		pll = intel_get_shared_dpll(intel_crtc);
		if (pll == NULL) {
			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
					 pipe_name(intel_crtc->pipe));
			return false;
932
		}
933

934
		intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
935 936 937 938 939
	}

	return true;
}

940 941 942 943 944 945 946 947 948 949 950 951 952 953 954
struct skl_wrpll_params {
	uint32_t        dco_fraction;
	uint32_t        dco_integer;
	uint32_t        qdiv_ratio;
	uint32_t        qdiv_mode;
	uint32_t        kdiv;
	uint32_t        pdiv;
	uint32_t        central_freq;
};

static void
skl_ddi_calculate_wrpll(int clock /* in Hz */,
			struct skl_wrpll_params *wrpll_params)
{
	uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
955 956 957
	uint64_t dco_central_freq[3] = {8400000000ULL,
					9000000000ULL,
					9600000000ULL};
958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
	uint32_t min_dco_deviation = 400;
	uint32_t min_dco_index = 3;
	uint32_t P0[4] = {1, 2, 3, 7};
	uint32_t P2[4] = {1, 2, 3, 5};
	bool found = false;
	uint32_t candidate_p = 0;
	uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
	uint32_t candidate_p2[3] = {0};
	uint32_t dco_central_freq_deviation[3];
	uint32_t i, P1, k, dco_count;
	bool retry_with_odd = false;
	uint64_t dco_freq;

	/* Determine P0, P1 or P2 */
	for (dco_count = 0; dco_count < 3; dco_count++) {
		found = false;
		candidate_p =
			div64_u64(dco_central_freq[dco_count], afe_clock);
		if (retry_with_odd == false)
			candidate_p = (candidate_p % 2 == 0 ?
				candidate_p : candidate_p + 1);

		for (P1 = 1; P1 < candidate_p; P1++) {
			for (i = 0; i < 4; i++) {
				if (!(P0[i] != 1 || P1 == 1))
					continue;

				for (k = 0; k < 4; k++) {
					if (P1 != 1 && P2[k] != 2)
						continue;

					if (candidate_p == P0[i] * P1 * P2[k]) {
						/* Found possible P0, P1, P2 */
						found = true;
						candidate_p0[dco_count] = P0[i];
						candidate_p1[dco_count] = P1;
						candidate_p2[dco_count] = P2[k];
						goto found;
					}

				}
			}
		}

found:
		if (found) {
			dco_central_freq_deviation[dco_count] =
				div64_u64(10000 *
					  abs_diff((candidate_p * afe_clock),
						   dco_central_freq[dco_count]),
					  dco_central_freq[dco_count]);

			if (dco_central_freq_deviation[dco_count] <
				min_dco_deviation) {
				min_dco_deviation =
					dco_central_freq_deviation[dco_count];
				min_dco_index = dco_count;
			}
		}

		if (min_dco_index > 2 && dco_count == 2) {
			retry_with_odd = true;
			dco_count = 0;
		}
	}

	if (min_dco_index > 2) {
		WARN(1, "No valid values found for the given pixel clock\n");
	} else {
		 wrpll_params->central_freq = dco_central_freq[min_dco_index];

		 switch (dco_central_freq[min_dco_index]) {
1030
		 case 9600000000ULL:
1031 1032
			wrpll_params->central_freq = 0;
			break;
1033
		 case 9000000000ULL:
1034 1035
			wrpll_params->central_freq = 1;
			break;
1036
		 case 8400000000ULL:
1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161
			wrpll_params->central_freq = 3;
		 }

		 switch (candidate_p0[min_dco_index]) {
		 case 1:
			wrpll_params->pdiv = 0;
			break;
		 case 2:
			wrpll_params->pdiv = 1;
			break;
		 case 3:
			wrpll_params->pdiv = 2;
			break;
		 case 7:
			wrpll_params->pdiv = 4;
			break;
		 default:
			WARN(1, "Incorrect PDiv\n");
		 }

		 switch (candidate_p2[min_dco_index]) {
		 case 5:
			wrpll_params->kdiv = 0;
			break;
		 case 2:
			wrpll_params->kdiv = 1;
			break;
		 case 3:
			wrpll_params->kdiv = 2;
			break;
		 case 1:
			wrpll_params->kdiv = 3;
			break;
		 default:
			WARN(1, "Incorrect KDiv\n");
		 }

		 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
		 wrpll_params->qdiv_mode =
			(wrpll_params->qdiv_ratio == 1) ? 0 : 1;

		 dco_freq = candidate_p0[min_dco_index] *
			 candidate_p1[min_dco_index] *
			 candidate_p2[min_dco_index] * afe_clock;

		/*
		* Intermediate values are in Hz.
		* Divide by MHz to match bsepc
		*/
		 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
		 wrpll_params->dco_fraction =
			 div_u64(((div_u64(dco_freq, 24) -
				   wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));

	}
}


static bool
skl_ddi_pll_select(struct intel_crtc *intel_crtc,
		   struct intel_encoder *intel_encoder,
		   int clock)
{
	struct intel_shared_dpll *pll;
	uint32_t ctrl1, cfgcr1, cfgcr2;

	/*
	 * See comment in intel_dpll_hw_state to understand why we always use 0
	 * as the DPLL id in this function.
	 */

	ctrl1 = DPLL_CTRL1_OVERRIDE(0);

	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
		struct skl_wrpll_params wrpll_params = { 0, };

		ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);

		skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);

		cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
			 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
			 wrpll_params.dco_integer;

		cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
			 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
			 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
			 wrpll_params.central_freq;
	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
		struct drm_encoder *encoder = &intel_encoder->base;
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

		switch (intel_dp->link_bw) {
		case DP_LINK_BW_1_62:
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
			break;
		case DP_LINK_BW_2_7:
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
			break;
		case DP_LINK_BW_5_4:
			ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
			break;
		}

		cfgcr1 = cfgcr2 = 0;
	} else /* eDP */
		return true;

	intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
	intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
	intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;

	pll = intel_get_shared_dpll(intel_crtc);
	if (pll == NULL) {
		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
				 pipe_name(intel_crtc->pipe));
		return false;
	}

	/* shared DPLL id 0 is DPLL 1 */
	intel_crtc->new_config->ddi_pll_sel = pll->id + 1;

	return true;
}
1162 1163 1164 1165 1166 1167 1168 1169 1170 1171

/*
 * Tries to find a *shared* PLL for the CRTC and store it in
 * intel_crtc->ddi_pll_sel.
 *
 * For private DPLLs, compute_config() should do the selection for us. This
 * function should be folded into compute_config() eventually.
 */
bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
{
1172
	struct drm_device *dev = intel_crtc->base.dev;
1173 1174 1175
	struct intel_encoder *intel_encoder =
		intel_ddi_get_crtc_new_encoder(intel_crtc);
	int clock = intel_crtc->new_config->port_clock;
1176

1177 1178 1179 1180
	if (IS_SKYLAKE(dev))
		return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
	else
		return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
1181 1182
}

1183 1184 1185 1186 1187
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1188
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1189 1190 1191
	int type = intel_encoder->type;
	uint32_t temp;

1192
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1193
		temp = TRANS_MSA_SYNC_CLK;
1194
		switch (intel_crtc->config.pipe_bpp) {
1195
		case 18:
1196
			temp |= TRANS_MSA_6_BPC;
1197 1198
			break;
		case 24:
1199
			temp |= TRANS_MSA_8_BPC;
1200 1201
			break;
		case 30:
1202
			temp |= TRANS_MSA_10_BPC;
1203 1204
			break;
		case 36:
1205
			temp |= TRANS_MSA_12_BPC;
1206 1207
			break;
		default:
1208
			BUG();
1209
		}
1210
		I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1211 1212 1213
	}
}

1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
	uint32_t temp;
	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
	if (state == true)
		temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
	else
		temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}

1229
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1230 1231 1232
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1233
	struct drm_encoder *encoder = &intel_encoder->base;
1234 1235
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1236
	enum pipe pipe = intel_crtc->pipe;
1237
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1238
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1239
	int type = intel_encoder->type;
1240 1241
	uint32_t temp;

1242 1243
	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
	temp = TRANS_DDI_FUNC_ENABLE;
1244
	temp |= TRANS_DDI_SELECT_PORT(port);
1245

1246
	switch (intel_crtc->config.pipe_bpp) {
1247
	case 18:
1248
		temp |= TRANS_DDI_BPC_6;
1249 1250
		break;
	case 24:
1251
		temp |= TRANS_DDI_BPC_8;
1252 1253
		break;
	case 30:
1254
		temp |= TRANS_DDI_BPC_10;
1255 1256
		break;
	case 36:
1257
		temp |= TRANS_DDI_BPC_12;
1258 1259
		break;
	default:
1260
		BUG();
1261
	}
1262

1263
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1264
		temp |= TRANS_DDI_PVSYNC;
1265
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1266
		temp |= TRANS_DDI_PHSYNC;
1267

1268 1269 1270
	if (cpu_transcoder == TRANSCODER_EDP) {
		switch (pipe) {
		case PIPE_A:
1271 1272 1273 1274
			/* On Haswell, can only use the always-on power well for
			 * eDP when not using the panel fitter, and when not
			 * using motion blur mitigation (which we don't
			 * support). */
1275 1276 1277
			if (IS_HASWELL(dev) &&
			    (intel_crtc->config.pch_pfit.enabled ||
			     intel_crtc->config.pch_pfit.force_thru))
1278 1279 1280
				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
			else
				temp |= TRANS_DDI_EDP_INPUT_A_ON;
1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
			break;
		case PIPE_B:
			temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
			break;
		case PIPE_C:
			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
			break;
		default:
			BUG();
			break;
		}
	}

1294
	if (type == INTEL_OUTPUT_HDMI) {
1295
		if (intel_crtc->config.has_hdmi_sink)
1296
			temp |= TRANS_DDI_MODE_SELECT_HDMI;
1297
		else
1298
			temp |= TRANS_DDI_MODE_SELECT_DVI;
1299

1300
	} else if (type == INTEL_OUTPUT_ANALOG) {
1301
		temp |= TRANS_DDI_MODE_SELECT_FDI;
1302
		temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
1303 1304 1305 1306 1307

	} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
		   type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320
		if (intel_dp->is_mst) {
			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
		} else
			temp |= TRANS_DDI_MODE_SELECT_DP_SST;

		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
	} else if (type == INTEL_OUTPUT_DP_MST) {
		struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;

		if (intel_dp->is_mst) {
			temp |= TRANS_DDI_MODE_SELECT_DP_MST;
		} else
			temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1321

1322
		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1323
	} else {
1324 1325
		WARN(1, "Invalid encoder type %d for pipe %c\n",
		     intel_encoder->type, pipe_name(pipe));
1326 1327
	}

1328
	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1329
}
1330

1331 1332
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
				       enum transcoder cpu_transcoder)
1333
{
1334
	uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1335 1336
	uint32_t val = I915_READ(reg);

1337
	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1338
	val |= TRANS_DDI_PORT_NONE;
1339
	I915_WRITE(reg, val);
1340 1341
}

1342 1343 1344 1345 1346 1347 1348 1349 1350
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
{
	struct drm_device *dev = intel_connector->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	int type = intel_connector->base.connector_type;
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
	enum pipe pipe = 0;
	enum transcoder cpu_transcoder;
1351
	enum intel_display_power_domain power_domain;
1352 1353
	uint32_t tmp;

1354
	power_domain = intel_display_port_power_domain(intel_encoder);
1355
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
1356 1357
		return false;

1358 1359 1360 1361 1362 1363
	if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
		return false;

	if (port == PORT_A)
		cpu_transcoder = TRANSCODER_EDP;
	else
1364
		cpu_transcoder = (enum transcoder) pipe;
1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376

	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));

	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
	case TRANS_DDI_MODE_SELECT_HDMI:
	case TRANS_DDI_MODE_SELECT_DVI:
		return (type == DRM_MODE_CONNECTOR_HDMIA);

	case TRANS_DDI_MODE_SELECT_DP_SST:
		if (type == DRM_MODE_CONNECTOR_eDP)
			return true;
		return (type == DRM_MODE_CONNECTOR_DisplayPort);
1377 1378 1379 1380
	case TRANS_DDI_MODE_SELECT_DP_MST:
		/* if the transcoder is in MST state then
		 * connector isn't connected */
		return false;
1381 1382 1383 1384 1385 1386 1387 1388 1389

	case TRANS_DDI_MODE_SELECT_FDI:
		return (type == DRM_MODE_CONNECTOR_VGA);

	default:
		return false;
	}
}

1390 1391 1392 1393 1394
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
			    enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1395
	enum port port = intel_ddi_get_encoder_port(encoder);
1396
	enum intel_display_power_domain power_domain;
1397 1398 1399
	u32 tmp;
	int i;

1400
	power_domain = intel_display_port_power_domain(encoder);
1401
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
1402 1403
		return false;

1404
	tmp = I915_READ(DDI_BUF_CTL(port));
1405 1406 1407 1408

	if (!(tmp & DDI_BUF_CTL_ENABLE))
		return false;

1409 1410
	if (port == PORT_A) {
		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1411

1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		case TRANS_DDI_EDP_INPUT_A_ON:
		case TRANS_DDI_EDP_INPUT_A_ONOFF:
			*pipe = PIPE_A;
			break;
		case TRANS_DDI_EDP_INPUT_B_ONOFF:
			*pipe = PIPE_B;
			break;
		case TRANS_DDI_EDP_INPUT_C_ONOFF:
			*pipe = PIPE_C;
			break;
		}

		return true;
	} else {
		for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
			tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));

			if ((tmp & TRANS_DDI_PORT_MASK)
			    == TRANS_DDI_SELECT_PORT(port)) {
1432 1433 1434
				if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
					return false;

1435 1436 1437
				*pipe = i;
				return true;
			}
1438 1439 1440
		}
	}

1441
	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1442

1443
	return false;
1444 1445
}

1446 1447 1448 1449 1450 1451
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
{
	struct drm_crtc *crtc = &intel_crtc->base;
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1452
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1453

1454 1455 1456
	if (cpu_transcoder != TRANSCODER_EDP)
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
			   TRANS_CLK_SEL_PORT(port));
1457 1458 1459 1460 1461
}

void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
{
	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1462
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1463

1464 1465 1466
	if (cpu_transcoder != TRANSCODER_EDP)
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
			   TRANS_CLK_SEL_DISABLED);
1467 1468
}

1469
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1470
{
1471
	struct drm_encoder *encoder = &intel_encoder->base;
1472 1473
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1474
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1475
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1476
	int type = intel_encoder->type;
1477

1478 1479
	if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1480
		intel_edp_panel_on(intel_dp);
1481
	}
1482

1483 1484 1485 1486
	if (IS_SKYLAKE(dev)) {
		uint32_t dpll = crtc->config.ddi_pll_sel;
		uint32_t val;

1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505
		/*
		 * DPLL0 is used for eDP and is the only "private" DPLL (as
		 * opposed to shared) on SKL
		 */
		if (type == INTEL_OUTPUT_EDP) {
			WARN_ON(dpll != SKL_DPLL0);

			val = I915_READ(DPLL_CTRL1);

			val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
				 DPLL_CTRL1_SSC(dpll) |
				 DPLL_CRTL1_LINK_RATE_MASK(dpll));
			val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6);

			I915_WRITE(DPLL_CTRL1, val);
			POSTING_READ(DPLL_CTRL1);
		}

		/* DDI -> PLL mapping  */
1506 1507 1508 1509 1510 1511 1512 1513
		val = I915_READ(DPLL_CTRL2);

		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
			DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
		val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));

		I915_WRITE(DPLL_CTRL2, val);
1514

1515 1516 1517 1518
	} else {
		WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
		I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
	}
1519

1520
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1521
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1522

1523
		intel_ddi_init_dp_buf_reg(intel_encoder);
1524 1525 1526 1527

		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
1528
		if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
1529
			intel_dp_stop_link_train(intel_dp);
1530 1531 1532 1533 1534 1535
	} else if (type == INTEL_OUTPUT_HDMI) {
		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

		intel_hdmi->set_infoframes(encoder,
					   crtc->config.has_hdmi_sink,
					   &crtc->config.adjusted_mode);
1536
	}
1537 1538
}

1539
static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1540 1541
{
	struct drm_encoder *encoder = &intel_encoder->base;
1542 1543
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1544
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1545
	int type = intel_encoder->type;
1546
	uint32_t val;
1547
	bool wait = false;
1548 1549 1550 1551 1552

	val = I915_READ(DDI_BUF_CTL(port));
	if (val & DDI_BUF_CTL_ENABLE) {
		val &= ~DDI_BUF_CTL_ENABLE;
		I915_WRITE(DDI_BUF_CTL(port), val);
1553
		wait = true;
1554
	}
1555

1556 1557 1558 1559 1560 1561 1562 1563
	val = I915_READ(DP_TP_CTL(port));
	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
	I915_WRITE(DP_TP_CTL(port), val);

	if (wait)
		intel_wait_ddi_buf_idle(dev_priv, port);

1564
	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1565
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1566
		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1567
		intel_edp_panel_vdd_on(intel_dp);
1568
		intel_edp_panel_off(intel_dp);
1569 1570
	}

1571 1572 1573 1574 1575
	if (IS_SKYLAKE(dev))
		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
					DPLL_CTRL2_DDI_CLK_OFF(port)));
	else
		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1576 1577
}

1578
static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1579
{
1580
	struct drm_encoder *encoder = &intel_encoder->base;
1581 1582
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1583
	struct drm_device *dev = encoder->dev;
1584
	struct drm_i915_private *dev_priv = dev->dev_private;
1585 1586
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
	int type = intel_encoder->type;
1587

1588
	if (type == INTEL_OUTPUT_HDMI) {
1589 1590 1591
		struct intel_digital_port *intel_dig_port =
			enc_to_dig_port(encoder);

1592 1593 1594 1595
		/* In HDMI/DVI mode, the port width, and swing/emphasis values
		 * are ignored so nothing special needs to be done besides
		 * enabling the port.
		 */
1596
		I915_WRITE(DDI_BUF_CTL(port),
1597 1598
			   intel_dig_port->saved_port_bits |
			   DDI_BUF_CTL_ENABLE);
1599 1600 1601
	} else if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

1602
		if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1603 1604
			intel_dp_stop_link_train(intel_dp);

1605
		intel_edp_backlight_on(intel_dp);
Rodrigo Vivi's avatar
Rodrigo Vivi committed
1606
		intel_psr_enable(intel_dp);
1607
	}
1608

1609
	if (intel_crtc->config.has_audio) {
1610
		intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1611
		intel_audio_codec_enable(intel_encoder);
1612
	}
1613 1614
}

1615
static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1616
{
1617
	struct drm_encoder *encoder = &intel_encoder->base;
1618 1619
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1620
	int type = intel_encoder->type;
1621 1622
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1623

1624
	if (intel_crtc->config.has_audio) {
1625
		intel_audio_codec_disable(intel_encoder);
1626 1627
		intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
	}
1628

1629 1630 1631
	if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

Rodrigo Vivi's avatar
Rodrigo Vivi committed
1632
		intel_psr_disable(intel_dp);
1633
		intel_edp_backlight_off(intel_dp);
1634
	}
1635
}
1636

1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684
static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
{
	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
	uint32_t cdctl = I915_READ(CDCLK_CTL);
	uint32_t linkrate;

	if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
		WARN(1, "LCPLL1 not enabled\n");
		return 24000; /* 24MHz is the cd freq with NSSC ref */
	}

	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
		return 540000;

	linkrate = (I915_READ(DPLL_CTRL1) &
		    DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;

	if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
	    linkrate == DPLL_CRTL1_LINK_RATE_1080) {
		/* vco 8640 */
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
		case CDCLK_FREQ_450_432:
			return 432000;
		case CDCLK_FREQ_337_308:
			return 308570;
		case CDCLK_FREQ_675_617:
			return 617140;
		default:
			WARN(1, "Unknown cd freq selection\n");
		}
	} else {
		/* vco 8100 */
		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
		case CDCLK_FREQ_450_432:
			return 450000;
		case CDCLK_FREQ_337_308:
			return 337500;
		case CDCLK_FREQ_675_617:
			return 675000;
		default:
			WARN(1, "Unknown cd freq selection\n");
		}
	}

	/* error case, do as if DPLL0 isn't enabled */
	return 24000;
}

1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704
static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
{
	uint32_t lcpll = I915_READ(LCPLL_CTL);
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;

	if (lcpll & LCPLL_CD_SOURCE_FCLK)
		return 800000;
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
		return 450000;
	else if (freq == LCPLL_CLK_FREQ_450)
		return 450000;
	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
		return 540000;
	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
		return 337500;
	else
		return 675000;
}

static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1705
{
1706
	struct drm_device *dev = dev_priv->dev;
1707
	uint32_t lcpll = I915_READ(LCPLL_CTL);
1708
	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1709

1710
	if (lcpll & LCPLL_CD_SOURCE_FCLK)
1711
		return 800000;
1712
	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1713
		return 450000;
1714
	else if (freq == LCPLL_CLK_FREQ_450)
1715
		return 450000;
1716
	else if (IS_HSW_ULT(dev))
1717 1718 1719 1720 1721 1722 1723 1724 1725
		return 337500;
	else
		return 540000;
}

int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;

1726 1727 1728
	if (IS_SKYLAKE(dev))
		return skl_get_cdclk_freq(dev_priv);

1729 1730 1731 1732 1733
	if (IS_BROADWELL(dev))
		return bdw_get_cdclk_freq(dev_priv);

	/* Haswell */
	return hsw_get_cdclk_freq(dev_priv);
1734 1735
}

1736 1737 1738
static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
			       struct intel_shared_dpll *pll)
{
1739
	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
1740 1741 1742 1743
	POSTING_READ(WRPLL_CTL(pll->id));
	udelay(20);
}

1744 1745 1746 1747 1748 1749 1750 1751 1752 1753
static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
				struct intel_shared_dpll *pll)
{
	uint32_t val;

	val = I915_READ(WRPLL_CTL(pll->id));
	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
	POSTING_READ(WRPLL_CTL(pll->id));
}

1754 1755 1756 1757 1758 1759
static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
				     struct intel_shared_dpll *pll,
				     struct intel_dpll_hw_state *hw_state)
{
	uint32_t val;

1760
	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1761 1762 1763 1764 1765 1766 1767 1768
		return false;

	val = I915_READ(WRPLL_CTL(pll->id));
	hw_state->wrpll = val;

	return val & WRPLL_PLL_ENABLE;
}

1769
static const char * const hsw_ddi_pll_names[] = {
1770 1771 1772 1773
	"WRPLL 1",
	"WRPLL 2",
};

1774
static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1775
{
1776 1777
	int i;

1778
	dev_priv->num_shared_dpll = 2;
1779

1780
	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1781 1782
		dev_priv->shared_dplls[i].id = i;
		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1783
		dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1784
		dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1785 1786
		dev_priv->shared_dplls[i].get_hw_state =
			hsw_ddi_pll_get_hw_state;
1787
	}
1788 1789
}

1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910
static const char * const skl_ddi_pll_names[] = {
	"DPLL 1",
	"DPLL 2",
	"DPLL 3",
};

struct skl_dpll_regs {
	u32 ctl, cfgcr1, cfgcr2;
};

/* this array is indexed by the *shared* pll id */
static const struct skl_dpll_regs skl_dpll_regs[3] = {
	{
		/* DPLL 1 */
		.ctl = LCPLL2_CTL,
		.cfgcr1 = DPLL1_CFGCR1,
		.cfgcr2 = DPLL1_CFGCR2,
	},
	{
		/* DPLL 2 */
		.ctl = WRPLL_CTL1,
		.cfgcr1 = DPLL2_CFGCR1,
		.cfgcr2 = DPLL2_CFGCR2,
	},
	{
		/* DPLL 3 */
		.ctl = WRPLL_CTL2,
		.cfgcr1 = DPLL3_CFGCR1,
		.cfgcr2 = DPLL3_CFGCR2,
	},
};

static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
			       struct intel_shared_dpll *pll)
{
	uint32_t val;
	unsigned int dpll;
	const struct skl_dpll_regs *regs = skl_dpll_regs;

	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
	dpll = pll->id + 1;

	val = I915_READ(DPLL_CTRL1);

	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
		 DPLL_CRTL1_LINK_RATE_MASK(dpll));
	val |= pll->config.hw_state.ctrl1 << (dpll * 6);

	I915_WRITE(DPLL_CTRL1, val);
	POSTING_READ(DPLL_CTRL1);

	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
	I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
	POSTING_READ(regs[pll->id].cfgcr1);
	POSTING_READ(regs[pll->id].cfgcr2);

	/* the enable bit is always bit 31 */
	I915_WRITE(regs[pll->id].ctl,
		   I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);

	if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
		DRM_ERROR("DPLL %d not locked\n", dpll);
}

static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
				struct intel_shared_dpll *pll)
{
	const struct skl_dpll_regs *regs = skl_dpll_regs;

	/* the enable bit is always bit 31 */
	I915_WRITE(regs[pll->id].ctl,
		   I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
	POSTING_READ(regs[pll->id].ctl);
}

static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
				     struct intel_shared_dpll *pll,
				     struct intel_dpll_hw_state *hw_state)
{
	uint32_t val;
	unsigned int dpll;
	const struct skl_dpll_regs *regs = skl_dpll_regs;

	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
		return false;

	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
	dpll = pll->id + 1;

	val = I915_READ(regs[pll->id].ctl);
	if (!(val & LCPLL_PLL_ENABLE))
		return false;

	val = I915_READ(DPLL_CTRL1);
	hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;

	/* avoid reading back stale values if HDMI mode is not enabled */
	if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
	}

	return true;
}

static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
{
	int i;

	dev_priv->num_shared_dpll = 3;

	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
		dev_priv->shared_dplls[i].id = i;
		dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
		dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
		dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
		dev_priv->shared_dplls[i].get_hw_state =
			skl_ddi_pll_get_hw_state;
	}
}

1911 1912 1913 1914 1915
void intel_ddi_pll_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t val = I915_READ(LCPLL_CTL);

1916 1917 1918 1919
	if (IS_SKYLAKE(dev))
		skl_shared_dplls_init(dev_priv);
	else
		hsw_shared_dplls_init(dev_priv);
1920

1921
	DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1922 1923
		      intel_ddi_get_cdclk_freq(dev_priv));

1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
	if (IS_SKYLAKE(dev)) {
		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
			DRM_ERROR("LCPLL1 is disabled\n");
	} else {
		/*
		 * The LCPLL register should be turned on by the BIOS. For now
		 * let's just check its state and print errors in case
		 * something is wrong.  Don't even try to turn it on.
		 */

		if (val & LCPLL_CD_SOURCE_FCLK)
			DRM_ERROR("CDCLK source is not LCPLL\n");
1936

1937 1938 1939
		if (val & LCPLL_PLL_DISABLE)
			DRM_ERROR("LCPLL is disabled\n");
	}
1940
}
1941 1942 1943

void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
{
1944 1945
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
1946
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1947
	enum port port = intel_dig_port->port;
1948
	uint32_t val;
1949
	bool wait = false;
1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968

	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
		val = I915_READ(DDI_BUF_CTL(port));
		if (val & DDI_BUF_CTL_ENABLE) {
			val &= ~DDI_BUF_CTL_ENABLE;
			I915_WRITE(DDI_BUF_CTL(port), val);
			wait = true;
		}

		val = I915_READ(DP_TP_CTL(port));
		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
		I915_WRITE(DP_TP_CTL(port), val);
		POSTING_READ(DP_TP_CTL(port));

		if (wait)
			intel_wait_ddi_buf_idle(dev_priv, port);
	}

1969
	val = DP_TP_CTL_ENABLE |
1970
	      DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1971 1972 1973 1974 1975 1976 1977
	if (intel_dp->is_mst)
		val |= DP_TP_CTL_MODE_MST;
	else {
		val |= DP_TP_CTL_MODE_SST;
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
	}
1978 1979 1980 1981 1982 1983 1984 1985 1986
	I915_WRITE(DP_TP_CTL(port), val);
	POSTING_READ(DP_TP_CTL(port));

	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
	POSTING_READ(DDI_BUF_CTL(port));

	udelay(600);
}
1987

1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013
void intel_ddi_fdi_disable(struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
	uint32_t val;

	intel_ddi_post_disable(intel_encoder);

	val = I915_READ(_FDI_RXA_CTL);
	val &= ~FDI_RX_ENABLE;
	I915_WRITE(_FDI_RXA_CTL, val);

	val = I915_READ(_FDI_RXA_MISC);
	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
	I915_WRITE(_FDI_RXA_MISC, val);

	val = I915_READ(_FDI_RXA_CTL);
	val &= ~FDI_PCDCLK;
	I915_WRITE(_FDI_RXA_CTL, val);

	val = I915_READ(_FDI_RXA_CTL);
	val &= ~FDI_RX_PLL_ENABLE;
	I915_WRITE(_FDI_RXA_CTL, val);
}

2014 2015
static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
{
2016 2017 2018 2019 2020 2021 2022 2023
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
	int type = intel_dig_port->base.type;

	if (type != INTEL_OUTPUT_DISPLAYPORT &&
	    type != INTEL_OUTPUT_EDP &&
	    type != INTEL_OUTPUT_UNKNOWN) {
		return;
	}
2024

2025
	intel_dp_hot_plug(intel_encoder);
2026 2027
}

2028 2029
void intel_ddi_get_config(struct intel_encoder *encoder,
			  struct intel_crtc_config *pipe_config)
2030 2031 2032 2033 2034
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
	u32 temp, flags = 0;
2035
	struct drm_device *dev = dev_priv->dev;
2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047

	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
	if (temp & TRANS_DDI_PHSYNC)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (temp & TRANS_DDI_PVSYNC)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

	pipe_config->adjusted_mode.flags |= flags;
2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064

	switch (temp & TRANS_DDI_BPC_MASK) {
	case TRANS_DDI_BPC_6:
		pipe_config->pipe_bpp = 18;
		break;
	case TRANS_DDI_BPC_8:
		pipe_config->pipe_bpp = 24;
		break;
	case TRANS_DDI_BPC_10:
		pipe_config->pipe_bpp = 30;
		break;
	case TRANS_DDI_BPC_12:
		pipe_config->pipe_bpp = 36;
		break;
	default:
		break;
	}
2065 2066 2067

	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
	case TRANS_DDI_MODE_SELECT_HDMI:
2068
		pipe_config->has_hdmi_sink = true;
2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079
	case TRANS_DDI_MODE_SELECT_DVI:
	case TRANS_DDI_MODE_SELECT_FDI:
		break;
	case TRANS_DDI_MODE_SELECT_DP_SST:
	case TRANS_DDI_MODE_SELECT_DP_MST:
		pipe_config->has_dp_encoder = true;
		intel_dp_get_m_n(intel_crtc, pipe_config);
		break;
	default:
		break;
	}
2080

2081
	if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2082
		temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2083
		if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2084 2085
			pipe_config->has_audio = true;
	}
2086

2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105
	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
2106

2107 2108 2109 2110
	if (INTEL_INFO(dev)->gen <= 8)
		hsw_ddi_clock_get(encoder, pipe_config);
	else
		skl_ddi_clock_get(encoder, pipe_config);
2111 2112
}

2113 2114 2115 2116 2117 2118
static void intel_ddi_destroy(struct drm_encoder *encoder)
{
	/* HDMI has nothing special to destroy, so we can go with this. */
	intel_dp_encoder_destroy(encoder);
}

2119 2120
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
				     struct intel_crtc_config *pipe_config)
2121
{
2122
	int type = encoder->type;
2123
	int port = intel_ddi_get_encoder_port(encoder);
2124

2125
	WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2126

2127 2128 2129
	if (port == PORT_A)
		pipe_config->cpu_transcoder = TRANSCODER_EDP;

2130
	if (type == INTEL_OUTPUT_HDMI)
2131
		return intel_hdmi_compute_config(encoder, pipe_config);
2132
	else
2133
		return intel_dp_compute_config(encoder, pipe_config);
2134 2135 2136 2137 2138 2139
}

static const struct drm_encoder_funcs intel_ddi_funcs = {
	.destroy = intel_ddi_destroy,
};

2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174
static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
{
	struct intel_connector *connector;
	enum port port = intel_dig_port->port;

	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
	if (!connector)
		return NULL;

	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
	if (!intel_dp_init_connector(intel_dig_port, connector)) {
		kfree(connector);
		return NULL;
	}

	return connector;
}

static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
{
	struct intel_connector *connector;
	enum port port = intel_dig_port->port;

	connector = kzalloc(sizeof(*connector), GFP_KERNEL);
	if (!connector)
		return NULL;

	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
	intel_hdmi_init_connector(intel_dig_port, connector);

	return connector;
}

2175 2176
void intel_ddi_init(struct drm_device *dev, enum port port)
{
2177
	struct drm_i915_private *dev_priv = dev->dev_private;
2178 2179 2180
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
2181 2182 2183 2184 2185 2186
	bool init_hdmi, init_dp;

	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
	if (!init_dp && !init_hdmi) {
2187
		DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2188 2189 2190 2191
			      port_name(port));
		init_hdmi = true;
		init_dp = true;
	}
2192

2193
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2194 2195 2196 2197 2198 2199 2200 2201 2202
	if (!intel_dig_port)
		return;

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, encoder, &intel_ddi_funcs,
			 DRM_MODE_ENCODER_TMDS);

2203
	intel_encoder->compute_config = intel_ddi_compute_config;
2204 2205 2206 2207 2208
	intel_encoder->enable = intel_enable_ddi;
	intel_encoder->pre_enable = intel_ddi_pre_enable;
	intel_encoder->disable = intel_disable_ddi;
	intel_encoder->post_disable = intel_ddi_post_disable;
	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2209
	intel_encoder->get_config = intel_ddi_get_config;
2210 2211

	intel_dig_port->port = port;
2212 2213 2214
	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
					  (DDI_BUF_PORT_REVERSAL |
					   DDI_A_4_LANES);
2215 2216

	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2217
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2218
	intel_encoder->cloneable = 0;
2219 2220
	intel_encoder->hot_plug = intel_ddi_hot_plug;

2221 2222 2223
	if (init_dp) {
		if (!intel_ddi_init_dp_connector(intel_dig_port))
			goto err;
2224

2225 2226 2227
		intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
		dev_priv->hpd_irq_port[port] = intel_dig_port;
	}
2228

2229 2230
	/* In theory we don't need the encoder->type check, but leave it just in
	 * case we have some really bad VBTs... */
2231 2232 2233
	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
		if (!intel_ddi_init_hdmi_connector(intel_dig_port))
			goto err;
2234
	}
2235 2236 2237 2238 2239 2240

	return;

err:
	drm_encoder_cleanup(encoder);
	kfree(intel_dig_port);
2241
}