GitLab

Drop no longer needed MAX macro, we have a max() function.

Corresponding to flashrom svn r601.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Also, list how many chips/chipsets/boards we support in 'flashrom -L'.

Corresponding to flashrom svn r599.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

There are multiple albatron pm266a boards which all share the same bios
image. This means that both the board enable and the subsystem ids are
exactly the same.

The board enable is the same as the epox EP-8K5A2, namely only raising
memw on the superio.

Corresponding to flashrom svn r581.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Mateusz Murawski <matowy@tlen.pl>

Corresponding to flashrom svn r572.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

I finally found the machine (doesn't belong to me) where I originally tested
this board as non-working and I can confirm that all operations work fine now
(since the nForce2 patch in r548).

Corresponding to flashrom svn r571.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

This makes FreeBSD happy.

Corresponding to flashrom svn r570.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Raises bits 0 and 2 on offset 0xE1 in the system control area of the
nvidia ck804 lpc.

Corresponding to flashrom svn r568.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Alexander Gordeev <lasaine@lvk.cs.msu.su>

 - ASUS A8N-SLI (reported by Ryan McLean <pvtryan100@googlemail.com>)

 - MSI/Medion MS-7255 (P4M890M) (reported by Jörg Schirottke <master@kanotix.com>)

Corresponding to flashrom svn r565.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Although the HT-1000 GPIOs are not SuperIO related, the share the same
index/data register access method.

Corresponding to flashrom svn r561.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

 - Add explicit installation instructions in the README.

 - Code cleanups, coding style fixes, drop dead code.

 - Drop duplicate board listings from -L output (some boards were explicitly
   recorded in boards_ok[] _and_ implicitly via the board-enables table.

 - Add MS-xxxx numbers to MSI boards where we can find that info.

 - Fix typo, "K8T Neo2" should have been "K8T Neo2-F" actually, at least
   according to the comment of w83627thf_gpio4_4_raise_2e() which says
   "Suited for: MSI K8T Neo2-F".

Corresponding to flashrom svn r554.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Marked as OK:

 - ASUS M2V (reported by Henri Valta <henri.valta@kemi.fi>)
   http://www.coreboot.org/pipermail/coreboot/2009-May/048674.html

 - Jetway J7F4K1G5D-PB (reported by Kevin O'Connor <kevin@koconnor.net>)

 - PC Engines Alix.3d3 (reported by Tobias Müller <Tobias_Mueller@twam.info>)
   http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html

 - MSI K7N2 (reported by Maciej Pijanka <maciej.pijanka@gmail.com>)
   http://www.coreboot.org/pipermail/coreboot/2009-May/048777.html

Marked as (so far) non-working:

 - DFI 855GME-MGF (reported by Tobias Müller <Tobias_Mueller@twam.info>)
   http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html

 - ASUS M3N78 Pro (reported by Piotr Esden-Tempski <esden@esden.net>)
   As discussed on IRC this is an MCP78 chipset with SPI translation apparently
   done in the southbridge, and we have no NVIDIA datasheets, of course. So the
   situation for this board will probably not change anytime soon.

 - MSI MS-6178 (reported by Uwe Hermann <uwe@hermann-uwe.de>)
   I tested write/erase will not work on this board, so a write-enable is
   needed. In _addition_, the board immediately powers off if you hot-unplug
   the PLCC chip, so I guess there's some SMI interference.

 - GIGABYTE GA-K8N-SLI (reported by Alexander Gordeev <lasaine@lvk.cs.msu.su>)
   This is currently being discussed on the mailing list (see
   http://www.coreboot.org/pipermail/coreboot/2009-May/048717.html

) and it's
   very likely that we'll be able to add a board-enable, so this board can be
   maked as OK soonish.

Corresponding to flashrom svn r553.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

While the other chipset enables for nvidia could potentially also work,
this one, by not touching other bits, seems like the safest solution.

Uwe tested this on his Asus A7N8X Deluxe, so hopefully the A7N8X-E
(reporter unknown) is now no longer an issue.

Corresponding to flashrom svn r548.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

We had duplicated code under different names and even open-coded some
functions in some places.

wbsio_read/regval -> sio_read wbsio_write/regwrite -> sio_write
wbsio_mask -> sio_mask

board_biostar_p4m80_m4 now uses existing IT87 functions.

Corresponding to flashrom svn r547.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>

Obvious typo due to inb/outb versus wbsio_ argument ordering confusion.

Corresponding to flashrom svn r546.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Thanks Christian Ruppert <spooky85@gmail.com> for testing on hardware.

(also: Fix a typo and some whitespace while I'm at it)

Corresponding to flashrom svn r545.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

 - Update manpage, we now report supported boards via -L.
 
 - Add some missing escaping for '-' characters in the manpage.

Corresponding to flashrom svn r543.

 - Shorten some of the really long device names, so that -L output looks
   nicer.
   
 - Display a "table header" for all entries/columns in -L output.
 
 - Make -L output tabular for all lists for better readability.
 
 - Do not print "unknown XXXX SPI chip" entries in -L output.
 
 - And random other cosmetics...
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>

 - ASUS P5B-Deluxe (reported by Andrew Paprocki)
 - ASUS P6T Deluxe V2 (reported by Aldrik Dunbar)
 - GIGABYTE GA-6ZMA (reported by Urja Rannikko)
 - Intel EP80759 (reported by Stephan GUILLOUX)
 - MSI MS-7345 (P35 Neo2-FIR) (reported by Onno)
 - MSI MS-7168 (Orion) (reported by ubuntosaure)
 - Supermicro H8QC8 (reported by Victor Zele)
 
Mark the following boards as 'known-bad' (they likely require a write-enable):

 - Abit IS-10 (reported by deejkuba)
 - ASUS P5B (reported by Henning Fleddermann)
 - ASUS P5BV-M (reported by Bernhard M. Wiedemann)
 - Boser HS-6637 (reported by Mark Robinson)
 
Also, mark the Winbond W39V040A as fully tested (report by ubuntosaure).

Corresponding to flashrom svn r542.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Thanks Michael Heimann for reporting.

The board was misidentified as a GIGABYTE GA-MA78G-DS3H though, as the
old PCI IDs and subsystem IDs of match. Thus, use differing ones for
both boards, which is not so easy. The only usable-looking difference
is in the SATA controller subsystem IDs. This should allow us to
properly detect both boards.

Corresponding to flashrom svn r534.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r533.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Thanks Myles Watson <mylesgw@gmail.com> for the report.

Corresponding to flashrom svn r532.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

 - Supported out of the box (no flash enables required)

 - Verifiably not yet working (unknown flash enable)

Also, move some structs to flash.h in preparation for later wiki
output support.

Corresponding to flashrom svn r523.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Build-tested on 32bit x86.

Corresponding to flashrom svn r521.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r490.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

This will allow generation of supported boards for wiki output to be
split to distinct columns.

Corresponding to flashrom svn r482.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

This is (among other things) useful/required for the -L output and the
upcoming wiki-syntax output of supported boards.

Corresponding to flashrom svn r474.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

This board uses IT8718F LPC->SPI translation for the flash chip.

Tested by Mateusz Murawski.

Corresponding to flashrom svn r438 and coreboot v2 svn r4161.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mateusz Murawski <matowy@tlen.pl>

This patch restores the pciid based board matching table. It makes this
table readable and hackable again, and the only disadvantage is that the
right margin is way beyond the rather dogmatic 80. All 0x0000 pci ids have
been string replaced by 0 to more easily spot missing ids, and extra
comments have been added to explain how the various entries are used.

Corresponding to flashrom svn r434 and coreboot v2 svn r4142.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>

It has SPI flash behind ITE8716 on LPC.

Corresponding to flashrom svn r430 and coreboot v2 svn r4132.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: illdred <illdred@gmail.com>

Tested on an iWILL DK8-HTX board.

Corresponding to flashrom svn r424 and coreboot v2 svn r4086.
Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

This is a BCM5785 based machine, WP# and TLB# need to be deasserted using
GPIO 2 and 5 from the PM registers of the southbridge.
This is very similar to the x3455 implementation.

Corresponding to flashrom svn r423 and coreboot v2 svn r4031.
Signed-off-by: Mondrian Nuessle <nuessle@uni-hd.de>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r414 and coreboot v2 svn r3927.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: David Tiemann <davidtiemann@gmail.com>

Corresponding to flashrom svn r405 and coreboot v2 svn r3911.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r403 and coreboot v2 svn r3909.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Similarly to flashchips array, this patch intends to make the table board_pciid_enables more readable.

Corresponding to flashrom svn r382 and coreboot v2 svn r3861.
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>

> What real problem does this solve?

1. Next time someone adds a new struct member, we avoid mistakes of
ordering of initializers
2. we avoid mistakes in the first place.

The .x = y stuff was added for a (good) reason, I think this is an
improvement.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge.
The board uses GIGABYTE's patented BIOS failover technology, and at this point
we do not know how to control which of the two chips flashrom actually hits.

Corresponding to flashrom svn r380 and coreboot v2 svn r3859.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>

There seem to be at least two versions of the board out there, and the
subsystem IDs changed between the versions.

Patch successfully tested on hardware.

Corresponding to flashrom svn r369 and coreboot v2 svn r3833.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r326 and coreboot v2 svn r3669.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

The KT4V is autodetected and supports the KT3 Ultra 2 with "-m msi:kt4v"
(but is not autodetected, yet).

Corresponding to flashrom svn r309 and coreboot v2 svn r3528.
Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

W39V040C does standard JEDEC commands except chip erase so add a small driver.
probe_w39v040c() prints the block lock pin status when a chip is found.

The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs.

Many thanks to Daniel McLellan for testing all of this on hardware!
Build tested by Uwe.

Corresponding to flashrom svn r304 and coreboot v2 svn r3431.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices
with their 1106:aa08 subsystem id:s for autodetection.

Corresponding to flashrom svn r297 and coreboot v2 svn r3413.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>