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Commit 24c1a160 authored by Carl-Daniel Hailfinger's avatar Carl-Daniel Hailfinger
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Refactor SuperIO accesses 


We had duplicated code under different names and even open-coded some
functions in some places.

wbsio_read/regval -> sio_read wbsio_write/regwrite -> sio_write
wbsio_mask -> sio_mask

board_biostar_p4m80_m4 now uses existing IT87 functions.

Corresponding to flashrom svn r547.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarLuc Verhaegen <libv@skynet.be>
parent 1fa38626
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Showing with 63 additions and 77 deletions
board_enable.c
View file @ 24c1a160
......@@ -44,26 +44,26 @@ void w836xx_ext_leave(uint16_t port)
OUTB(0xAA, port);
}
/* General functions for reading/writing Winbond Super I/Os. */
unsigned char wbsio_read(uint16_t index, uint8_t reg)
/* Generic Super I/O helper functions */
uint8_t sio_read(uint16_t port, uint8_t reg)
{
OUTB(reg, index);
return INB(index + 1);
OUTB(reg, port);
return INB(port + 1);
}
void wbsio_write(uint16_t index, uint8_t reg, uint8_t data)
void sio_write(uint16_t port, uint8_t reg, uint8_t data)
{
OUTB(reg, index);
OUTB(data, index + 1);
OUTB(reg, port);
OUTB(data, port + 1);
}
void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
{
uint8_t tmp;
OUTB(reg, index);
tmp = INB(index + 1) & ~mask;
OUTB(tmp | (data & mask), index + 1);
OUTB(reg, port);
tmp = INB(port + 1) & ~mask;
OUTB(tmp | (data & mask), port + 1);
}
/**
......@@ -73,30 +73,30 @@ void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
* - Agami Aruma
* - IWILL DK8-HTX
*/
static int w83627hf_gpio24_raise(uint16_t index, const char *name)
static int w83627hf_gpio24_raise(uint16_t port, const char *name)
{
w836xx_ext_enter(index);
w836xx_ext_enter(port);
/* Is this the W83627HF? */
if (wbsio_read(index, 0x20) != 0x52) { /* Super I/O device ID reg. */
if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
name, wbsio_read(index, 0x20));
w836xx_ext_leave(index);
name, sio_read(port, 0x20));
w836xx_ext_leave(port);
return -1;
}
/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
wbsio_mask(index, 0x2B, 0x10, 0x10);
sio_mask(port, 0x2B, 0x10, 0x10);
/* Select logical device 8: GPIO port 2 */
wbsio_write(index, 0x07, 0x08);
sio_write(port, 0x07, 0x08);
wbsio_mask(index, 0x30, 0x01, 0x01); /* Activate logical device. */
wbsio_mask(index, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
wbsio_mask(index, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
wbsio_mask(index, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
w836xx_ext_leave(index);
w836xx_ext_leave(port);
return 0;
}
......@@ -113,27 +113,27 @@ static int w83627hf_gpio24_raise_2e(const char *name)
* - MSI K8T Neo2-F
* - MSI K8N-NEO3
*/
static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
{
w836xx_ext_enter(index);
w836xx_ext_enter(port);
/* Is this the W83627THF? */
if (wbsio_read(index, 0x20) != 0x82) { /* Super I/O device ID reg. */
if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
name, wbsio_read(index, 0x20));
w836xx_ext_leave(index);
name, sio_read(port, 0x20));
w836xx_ext_leave(port);
return -1;
}
/* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
wbsio_write(index, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
wbsio_mask(index, 0x30, 0x02, 0x02); /* Activate logical device. */
wbsio_mask(index, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
wbsio_mask(index, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
wbsio_mask(index, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
w836xx_ext_leave(index);
w836xx_ext_leave(port);
return 0;
}
......@@ -151,14 +151,14 @@ static int w83627thf_gpio4_4_raise_4e(const char *name)
/**
* w83627: Enable MEMW# and set ROM size to max.
*/
static void w836xx_memw_enable(uint16_t index)
static void w836xx_memw_enable(uint16_t port)
{
w836xx_ext_enter(index);
if (!(wbsio_read(index, 0x24) & 0x02)) { /* Flash ROM enabled? */
w836xx_ext_enter(port);
if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
/* Enable MEMW# and set ROM size select to max. (4M). */
wbsio_mask(index, 0x24, 0x28, 0x28);
sio_mask(port, 0x24, 0x28, 0x28);
}
w836xx_ext_leave(index);
w836xx_ext_leave(port);
}
/**
......@@ -595,21 +595,18 @@ static int board_kontron_986lcd_m(const char *name)
static int board_biostar_p4m80_m4(const char *name)
{
/* enter IT87xx conf mode */
OUTB(0x87, 0x2e);
OUTB(0x01, 0x2e);
OUTB(0x55, 0x2e);
OUTB(0x55, 0x2e);
enter_conf_mode_ite(0x2e);
/* select right flash chip */
wbsio_mask(0x2e, 0x22, 0x80, 0x80);
sio_mask(0x2e, 0x22, 0x80, 0x80);
/* bit 3: flash chip write enable
* bit 7: map flash chip at 1MB-128K (why though? ignoring this.)
*/
wbsio_mask(0x2e, 0x24, 0x04, 0x04);
sio_mask(0x2e, 0x24, 0x04, 0x04);
/* exit IT87xx conf mode */
wbsio_write(0x2e, 0x02, 0x02);
exit_conf_mode_ite(0x2e);
return 0;
}
......
flash.h
View file @ 24c1a160
......@@ -579,9 +579,9 @@ void print_supported_pcidevs(struct pcidev_status *devs);
/* board_enable.c */
void w836xx_ext_enter(uint16_t port);
void w836xx_ext_leave(uint16_t port);
unsigned char wbsio_read(uint16_t index, uint8_t reg);
void wbsio_write(uint16_t index, uint8_t reg, uint8_t data);
void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask);
uint8_t sio_read(uint16_t port, uint8_t reg);
void sio_write(uint16_t port, uint8_t reg, uint8_t data);
void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
int board_flash_enable(const char *vendor, const char *part);
void print_supported_boards(void);
......@@ -737,6 +737,8 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf);
/* it87spi.c */
extern uint16_t it8716f_flashport;
void enter_conf_mode_ite(uint16_t port);
void exit_conf_mode_ite(uint16_t port);
int it87xx_probe_spi_flash(const char *name);
int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr);
......
it87spi.c
View file @ 24c1a160
......@@ -34,23 +34,10 @@ uint16_t it8716f_flashport = 0;
/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
int fast_spi = 1;
/* Generic Super I/O helper functions */
uint8_t regval(uint16_t port, uint8_t reg)
{
OUTB(reg, port);
return INB(port + 1);
}
void regwrite(uint16_t port, uint8_t reg, uint8_t val)
{
OUTB(reg, port);
OUTB(val, port + 1);
}
/* Helper functions for most recent ITE IT87xx Super I/O chips */
#define CHIP_ID_BYTE1_REG 0x20
#define CHIP_ID_BYTE2_REG 0x21
static void enter_conf_mode_ite(uint16_t port)
void enter_conf_mode_ite(uint16_t port)
{
OUTB(0x87, port);
OUTB(0x01, port);
......@@ -61,9 +48,9 @@ static void enter_conf_mode_ite(uint16_t port)
OUTB(0xaa, port);
}
static void exit_conf_mode_ite(uint16_t port)
void exit_conf_mode_ite(uint16_t port)
{
regwrite(port, 0x02, 0x02);
sio_write(port, 0x02, 0x02);
}
static uint16_t find_ite_spi_flash_port(uint16_t port)
......@@ -73,13 +60,13 @@ static uint16_t find_ite_spi_flash_port(uint16_t port)
enter_conf_mode_ite(port);
id = regval(port, CHIP_ID_BYTE1_REG) << 8;
id |= regval(port, CHIP_ID_BYTE2_REG);
id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
id |= sio_read(port, CHIP_ID_BYTE2_REG);
/* TODO: Handle more IT87xx if they support flash translation */
if (0x8716 == id || 0x8718 == id) {
/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
tmp = regval(port, 0x24) & 0xFE;
tmp = sio_read(port, 0x24) & 0xFE;
printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
......@@ -94,13 +81,13 @@ static uint16_t find_ite_spi_flash_port(uint16_t port)
if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
printf("Enabling LPC write to serial flash\n");
tmp |= 1 << 4;
regwrite(port, 0x24, tmp);
sio_write(port, 0x24, tmp);
}
printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
/* LDN 0x7, reg 0x64/0x65 */
regwrite(port, 0x07, 0x7);
flashport = regval(port, 0x64) << 8;
flashport |= regval(port, 0x65);
sio_write(port, 0x07, 0x7);
flashport = sio_read(port, 0x64) << 8;
flashport |= sio_read(port, 0x65);
}
exit_conf_mode_ite(port);
return flashport;
......
wbsio_spi.c
View file @ 24c1a160
......@@ -32,24 +32,24 @@ static uint16_t wbsio_get_spibase(uint16_t port)
uint16_t flashport = 0;
w836xx_ext_enter(port);
id = wbsio_read(port, 0x20);
id = sio_read(port, 0x20);
if (id != 0xa0) {
fprintf(stderr, "\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
goto done;
}
if (0 == (wbsio_read(port, 0x24) & 2)) {
if (0 == (sio_read(port, 0x24) & 2)) {
fprintf(stderr, "\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
goto done;
}
wbsio_write(port, 0x07, 0x06);
if (0 == (wbsio_read(port, 0x30) & 1)) {
sio_write(port, 0x07, 0x06);
if (0 == (sio_read(port, 0x30) & 1)) {
fprintf(stderr, "\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
goto done;
}
flashport = (wbsio_read(port, 0x62) << 8) | wbsio_read(port, 0x63);
flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63);
done:
w836xx_ext_leave(port);
......
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