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Commit dac3f0da authored by Raptor Engineering Development Team's avatar Raptor Engineering Development Team
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main.c: Migrate #ifdef-controlled code to #if control 

This resolves issues where the #ifdef-controlled code could
counter-intuitively be activated even when the controlling #define
statement was set to 0.
parent 0715b617
no-dram i2c-debug ipl-debug meklort/test-boot
4 merge requests!17Add optional DRAM-free mode,!16Add I2C debug commands to console,!13WIP: ci: Build and prepare the fpga with the bootrom.,!4Add triple read mode for SPI hardware / HDL diagnostics
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main.c
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include <uart.h> #include <uart.h>
#ifdef WITH_SPI #if (WITH_SPI)
#include "micron_n25q_flash.h" #include "micron_n25q_flash.h"
#include "tercel_spi.h" #include "tercel_spi.h"
#endif #endif
...@@ -27,13 +27,13 @@ ...@@ -27,13 +27,13 @@
#include "opencores_i2c.h" #include "opencores_i2c.h"
// Performance controls // Performance controls
#define ENABLE_LPC_FW_CYCLE_IRQ_HANDLER #define ENABLE_LPC_FW_CYCLE_IRQ_HANDLER 1 // Set to 1 to enable LPC master transfer interrupts to the BMC soft core
#define ENABLE_LPC_FW_CYCLE_DMA #define ENABLE_LPC_FW_CYCLE_DMA 1 // Set to 1 to allow the LPC master to DMA data to/from the Wishbone bus
#define ALLOW_SPI_QUAD_MODE 1 #define ALLOW_SPI_QUAD_MODE 1 // Set to 1 to allow quad-mode SPI transfers if the hardware supports them
// Debug knobs // Debug knobs
// #define DEBUG_HOST_SPI_FLASH_READ 1 #define DEBUG_HOST_SPI_FLASH_READ 0 // Set to 1 to enable verbose logging of SPI flash read process
#define SPI_FLASH_TRIPLE_READ 0 // Set to 1 to enable triple-read data checks (slow) #define SPI_FLASH_TRIPLE_READ 0 // Set to 1 to enable triple-read data checks (slow)
// General RCS platform registers // General RCS platform registers
#define HOST_PLATFORM_FPGA_I2C_REG_STATUS 0x7 #define HOST_PLATFORM_FPGA_I2C_REG_STATUS 0x7
...@@ -313,7 +313,7 @@ static void set_lpc_slave_irq_enable(uint8_t enabled) ...@@ -313,7 +313,7 @@ static void set_lpc_slave_irq_enable(uint8_t enabled)
void lpc_slave_isr(void) void lpc_slave_isr(void)
{ {
#ifdef ENABLE_LPC_FW_CYCLE_IRQ_HANDLER #if (ENABLE_LPC_FW_CYCLE_IRQ_HANDLER)
int byte; int byte;
int word; int word;
#endif #endif
...@@ -334,7 +334,7 @@ void lpc_slave_isr(void) ...@@ -334,7 +334,7 @@ void lpc_slave_isr(void)
// Master IRQ asserted // Master IRQ asserted
// Determine source within the LPC slave core // Determine source within the LPC slave core
status4_reg = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_STATUS4); status4_reg = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_STATUS4);
#ifdef ENABLE_LPC_FW_CYCLE_IRQ_HANDLER #if (ENABLE_LPC_FW_CYCLE_IRQ_HANDLER)
if (status4_reg & AQUILA_LPC_FW_CYCLE_IRQ_ASSERTED) if (status4_reg & AQUILA_LPC_FW_CYCLE_IRQ_ASSERTED)
{ {
// Firmware cycle request has caused IRQ assert // Firmware cycle request has caused IRQ assert
...@@ -973,7 +973,7 @@ static void process_host_to_bmc_ipmi_bt_transactions(void) ...@@ -973,7 +973,7 @@ static void process_host_to_bmc_ipmi_bt_transactions(void)
break; break;
} }
#ifdef ENABLE_LPC_FW_CYCLE_DMA #if (ENABLE_LPC_FW_CYCLE_DMA)
// Disable DMA engine // Disable DMA engine
dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG1); dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG1);
dword &= ~((1 & AQUILA_LPC_CTL_EN_FW_DMA_R_MASK) << AQUILA_LPC_CTL_EN_FW_DMA_R_SHIFT); dword &= ~((1 & AQUILA_LPC_CTL_EN_FW_DMA_R_MASK) << AQUILA_LPC_CTL_EN_FW_DMA_R_SHIFT);
...@@ -1170,7 +1170,7 @@ static void process_host_to_bmc_ipmi_bt_transactions(void) ...@@ -1170,7 +1170,7 @@ static void process_host_to_bmc_ipmi_bt_transactions(void)
} }
} }
#ifndef ENABLE_LPC_FW_CYCLE_IRQ_HANDLER #if !(ENABLE_LPC_FW_CYCLE_IRQ_HANDLER)
static uint32_t previous_fw_read_address; static uint32_t previous_fw_read_address;
#endif #endif
...@@ -1305,7 +1305,7 @@ static void run_pre_ipl_bmc_peripheral_setup(void) ...@@ -1305,7 +1305,7 @@ static void run_pre_ipl_bmc_peripheral_setup(void)
dword |= ((1 & AQUILA_LPC_CTL_EN_IPMI_BT_IRQ_MASK) << AQUILA_LPC_CTL_EN_IPMI_BT_IRQ_SHIFT); dword |= ((1 & AQUILA_LPC_CTL_EN_IPMI_BT_IRQ_MASK) << AQUILA_LPC_CTL_EN_IPMI_BT_IRQ_SHIFT);
write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1, dword); write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1, dword);
#ifdef ENABLE_LPC_FW_CYCLE_IRQ_HANDLER #if (ENABLE_LPC_FW_CYCLE_IRQ_HANDLER)
// Enable LPC firmware cycle IRQ // Enable LPC firmware cycle IRQ
dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1); dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1);
dword |= ((1 & AQUILA_LPC_CTL_EN_FW_CYCLE_IRQ_MASK) << AQUILA_LPC_CTL_EN_FW_CYCLE_IRQ_SHIFT); dword |= ((1 & AQUILA_LPC_CTL_EN_FW_CYCLE_IRQ_MASK) << AQUILA_LPC_CTL_EN_FW_CYCLE_IRQ_SHIFT);
...@@ -1320,7 +1320,7 @@ static void run_pre_ipl_bmc_peripheral_setup(void) ...@@ -1320,7 +1320,7 @@ static void run_pre_ipl_bmc_peripheral_setup(void)
hiomap_config.window_type = HIOMAP_WINDOW_TYPE_READ; hiomap_config.window_type = HIOMAP_WINDOW_TYPE_READ;
hiomap_config.dirty_range_count = 0; hiomap_config.dirty_range_count = 0;
#ifdef ENABLE_LPC_FW_CYCLE_DMA #if (ENABLE_LPC_FW_CYCLE_DMA)
// Configure and enable LPC firmware cycle DMA // Configure and enable LPC firmware cycle DMA
// Set up default window with address masking based on physical ROM size // Set up default window with address masking based on physical ROM size
write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG2, (uintptr_t)host_flash_buffer); write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG2, (uintptr_t)host_flash_buffer);
...@@ -1363,7 +1363,7 @@ static void run_post_shutdown_bmc_peripheral_teardown(void) ...@@ -1363,7 +1363,7 @@ static void run_post_shutdown_bmc_peripheral_teardown(void)
} }
write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_IPMI_BT_STATUS, dword); write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_IPMI_BT_STATUS, dword);
#ifdef ENABLE_LPC_FW_CYCLE_DMA #if (ENABLE_LPC_FW_CYCLE_DMA)
// Disable DMA engine // Disable DMA engine
dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG1); dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG1);
dword &= ~((1 & AQUILA_LPC_CTL_EN_FW_DMA_R_MASK) << AQUILA_LPC_CTL_EN_FW_DMA_R_SHIFT); dword &= ~((1 & AQUILA_LPC_CTL_EN_FW_DMA_R_MASK) << AQUILA_LPC_CTL_EN_FW_DMA_R_SHIFT);
...@@ -1371,7 +1371,7 @@ static void run_post_shutdown_bmc_peripheral_teardown(void) ...@@ -1371,7 +1371,7 @@ static void run_post_shutdown_bmc_peripheral_teardown(void)
write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG1, dword); write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG1, dword);
#endif #endif
#ifdef ENABLE_LPC_FW_CYCLE_IRQ_HANDLER #if (ENABLE_LPC_FW_CYCLE_IRQ_HANDLER)
// Disable LPC firmware cycle IRQ // Disable LPC firmware cycle IRQ
dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1); dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1);
dword &= ~((1 & AQUILA_LPC_CTL_EN_FW_CYCLE_IRQ_MASK) << AQUILA_LPC_CTL_EN_FW_CYCLE_IRQ_SHIFT); dword &= ~((1 & AQUILA_LPC_CTL_EN_FW_CYCLE_IRQ_MASK) << AQUILA_LPC_CTL_EN_FW_CYCLE_IRQ_SHIFT);
...@@ -1703,7 +1703,7 @@ static void host_background_service_task_event_loop(void) ...@@ -1703,7 +1703,7 @@ static void host_background_service_task_event_loop(void)
uint32_t address; uint32_t address;
uint8_t write_not_read; uint8_t write_not_read;
uint32_t dword; uint32_t dword;
#ifndef ENABLE_LPC_FW_CYCLE_IRQ_HANDLER #if !(ENABLE_LPC_FW_CYCLE_IRQ_HANDLER)
int byte; int byte;
int word; int word;
uint32_t physical_flash_address; uint32_t physical_flash_address;
...@@ -1728,7 +1728,7 @@ static void host_background_service_task_event_loop(void) ...@@ -1728,7 +1728,7 @@ static void host_background_service_task_event_loop(void)
uint32_t status2_reg = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_STATUS2); uint32_t status2_reg = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_STATUS2);
address = (status2_reg >> AQUILA_LPC_STATUS_ACT_ADDR_SHIFT) & AQUILA_LPC_STATUS_ACT_ADDR_MASK; address = (status2_reg >> AQUILA_LPC_STATUS_ACT_ADDR_SHIFT) & AQUILA_LPC_STATUS_ACT_ADDR_MASK;
write_not_read = (status1_reg >> AQUILA_LPC_STATUS_CYC_WNR_SHIFT) & AQUILA_LPC_STATUS_CYC_WNR_MASK; write_not_read = (status1_reg >> AQUILA_LPC_STATUS_CYC_WNR_SHIFT) & AQUILA_LPC_STATUS_CYC_WNR_MASK;
#ifndef ENABLE_LPC_FW_CYCLE_IRQ_HANDLER #if !(ENABLE_LPC_FW_CYCLE_IRQ_HANDLER)
if (((status1_reg >> AQUILA_LPC_STATUS_CYCLE_TYPE_SHIFT) & AQUILA_LPC_STATUS_CYCLE_TYPE_MASK) == AQUILA_LPC_STATUS_CYCLE_TYPE_FW) if (((status1_reg >> AQUILA_LPC_STATUS_CYCLE_TYPE_SHIFT) & AQUILA_LPC_STATUS_CYCLE_TYPE_MASK) == AQUILA_LPC_STATUS_CYCLE_TYPE_FW)
{ {
uint8_t fw_cycle_idsel = (status1_reg >> AQUILA_LPC_STATUS_FW_CYCLE_IDSEL_SHIFT) & AQUILA_LPC_STATUS_FW_CYCLE_IDSEL_MASK; uint8_t fw_cycle_idsel = (status1_reg >> AQUILA_LPC_STATUS_FW_CYCLE_IDSEL_SHIFT) & AQUILA_LPC_STATUS_FW_CYCLE_IDSEL_MASK;
...@@ -2261,7 +2261,7 @@ static void memset32(uint32_t *destination, uint32_t value, int words) ...@@ -2261,7 +2261,7 @@ static void memset32(uint32_t *destination, uint32_t value, int words)
} }
} }
#ifdef WITH_SPI #if (WITH_SPI)
static uint32_t read_host_spi_flash_id(void) static uint32_t read_host_spi_flash_id(void)
{ {
uint32_t flash_id = 0; uint32_t flash_id = 0;
...@@ -2419,7 +2419,7 @@ static int host_spi_flash_init(void) ...@@ -2419,7 +2419,7 @@ static int host_spi_flash_init(void)
} }
#endif #endif
#ifdef WITH_SPI #if (WITH_SPI)
#define SPI_READ_TRANSFER_SIZE (1 * 1024 * 1024LL) #define SPI_READ_TRANSFER_SIZE (1 * 1024 * 1024LL)
int copy_spi_flash_to_internal_buffer(uintptr_t flash_data, uintptr_t flash_ctl, uint8_t *buffer) int copy_spi_flash_to_internal_buffer(uintptr_t flash_data, uintptr_t flash_ctl, uint8_t *buffer)
{ {
...@@ -2579,7 +2579,7 @@ int main(void) ...@@ -2579,7 +2579,7 @@ int main(void)
display_character('1', 0); // STATUS CODE: 1 display_character('1', 0); // STATUS CODE: 1
#ifdef WITH_SPI #if (WITH_SPI)
host_spi_flash_init(); host_spi_flash_init();
// Detect and print attached host SPI Flash ID // Detect and print attached host SPI Flash ID
...@@ -2591,7 +2591,7 @@ int main(void) ...@@ -2591,7 +2591,7 @@ int main(void)
// Copy external SPI Flash ROM contents to internal host SPI Flash ROM buffer // Copy external SPI Flash ROM contents to internal host SPI Flash ROM buffer
copy_spi_flash_to_internal_buffer(HOSTSPIFLASH_BASE, HOSTSPIFLASHCFG_BASE, host_flash_buffer); copy_spi_flash_to_internal_buffer(HOSTSPIFLASH_BASE, HOSTSPIFLASHCFG_BASE, host_flash_buffer);
#ifdef DEBUG_HOST_SPI_FLASH_READ #if (DEBUG_HOST_SPI_FLASH_READ)
printf("host_flash_buffer: %p First 1KB:\n", host_flash_buffer); printf("host_flash_buffer: %p First 1KB:\n", host_flash_buffer);
int byte = 0; int byte = 0;
int row = 0; int row = 0;
......
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