- 27 Feb, 2020 7 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
Ease switching between ddram_32 and ddram_64.
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Florent Kermarrec authored
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- 26 Feb, 2020 3 commits
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Piotr Binkowski authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 25 Feb, 2020 5 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 24 Feb, 2020 1 commit
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Fei Gao authored
add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
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- 23 Feb, 2020 1 commit
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Gwenhael Goavec-Merou authored
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- 12 Feb, 2020 1 commit
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Leonardo Romor authored
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- 11 Feb, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
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- 03 Feb, 2020 2 commits
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Florent Kermarrec authored
We initially wanted to provide different level of support for the platforms/targets, mainly to avoid too much maintenance and let each contributor update its contributed platforms and targets, but it's easier to update all platforms/targets all-together when LiteX evolves or changes (and that's what has been done on litex-boards since the creation of the repository). So let just simplify things and avoid this differentiation.
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Sean Cross authored
Things weren't quite right for adding a CPU. This fixes that by correcting the placer arguments, memory map, and USB type. Signed-off-by: Sean Cross <sean@xobs.io>
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- 31 Jan, 2020 2 commits
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Florent Kermarrec authored
de10nano: cleanup a bit, rename SDRAMSoC to MiSTerSDRAMSoC and argument to --with-mister-sdram to make it clear that it's using the MiSTer SDRAM extension board.
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Florent Kermarrec authored
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- 30 Jan, 2020 2 commits
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Paul Sajna authored
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Paul Sajna authored
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- 29 Jan, 2020 2 commits
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Paul Sajna authored
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Paul Sajna authored
add iostandard to hdmi
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- 23 Jan, 2020 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 22 Jan, 2020 7 commits
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Florent Kermarrec authored
Tested with: ./colorlight_5a_75b.py --cpu-type=picorv32 --uart-name=crossover --with-etherbone --csr-csv=csr.csv Load with following script: #!/usr/bin/env python3 # Load --------------------------------------------------------------------------------------------- def load(): import os f = open("openocd.cfg", "w") f.write( """ interface ftdi ftdi_vid_pid 0x0403 0x6011 ftdi_channel 0 ftdi_layout_init 0x0098 0x008b reset_config none adapter_khz 25000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043 """) f.close() os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"") exit() if __name__ == "__main__": load() Then start lxserver: lxserver --udp And run following script: #!/usr/bin/env python3 import sys from litex import RemoteClient wb = RemoteClient() wb.open() # # # while True: if wb.regs.uart_xover_rxempty.read() == 0: print(chr(wb.regs.uart_xover_rxtx.read()), end="") sys.stdout.flush() # # # wb.close()
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 21 Jan, 2020 1 commit
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Florent Kermarrec authored
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- 18 Jan, 2020 1 commit
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Florent Kermarrec authored
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