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Timothy Pearson
litex-boards
Commits
55c0b781
Commit
55c0b781
authored
4 years ago
by
Florent Kermarrec
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colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt)
parent
4fb89fc9
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litex_boards/partner/targets/colorlight_5a_75b.py
litex_boards/partner/targets/colorlight_5a_75b.py
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litex_boards/partner/targets/colorlight_5a_75b.py
View file @
55c0b781
...
@@ -68,8 +68,8 @@ class EtherboneSoC(BaseSoC):
...
@@ -68,8 +68,8 @@ class EtherboneSoC(BaseSoC):
self
.
submodules
.
ethphy
=
LiteEthPHYRGMII
(
self
.
submodules
.
ethphy
=
LiteEthPHYRGMII
(
clock_pads
=
self
.
platform
.
request
(
"eth_clocks"
,
eth_phy
),
clock_pads
=
self
.
platform
.
request
(
"eth_clocks"
,
eth_phy
),
pads
=
self
.
platform
.
request
(
"eth"
,
eth_phy
),
pads
=
self
.
platform
.
request
(
"eth"
,
eth_phy
),
tx_delay
=
0e-9
,
#
No
FPGA delay (Clk
/Data
delay added by
PCB/
PHY)
tx_delay
=
0e-9
,
#
0ns
FPGA delay (Clk delay added by PHY)
rx_delay
=
0
e-9
)
#
No
FPGA delay
(Clk/Data delay added by PCB/PHY)
rx_delay
=
2
e-9
)
#
2ns
FPGA delay
to compensate Clk routing to IDDRX1F
self
.
add_csr
(
"ethphy"
)
self
.
add_csr
(
"ethphy"
)
# core
# core
self
.
submodules
.
ethcore
=
LiteEthUDPIPCore
(
self
.
submodules
.
ethcore
=
LiteEthUDPIPCore
(
...
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