- 29 Oct, 2019 2 commits
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Gabriel Somlo authored
Sync up with litex commit #201218b2c.
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Gabriel Somlo authored
Sync up with litex commit #ae9c25b74.
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- 13 Oct, 2019 3 commits
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Florent Kermarrec authored
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Steven Osborn authored
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Steven Osborn authored
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- 11 Oct, 2019 2 commits
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Sean Cross authored
This connector is for the six "debug" pins on the Raspberry Pi header. Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross authored
The D3 and D4 pins were swapped around, leading to interesting issues. Signed-off-by: Sean Cross <sean@xobs.io>
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- 09 Oct, 2019 1 commit
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Florent Kermarrec authored
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- 27 Sep, 2019 1 commit
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Sean Cross authored
Signed-off-by: Sean Cross <sean@xobs.io>
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- 25 Sep, 2019 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 17 Sep, 2019 3 commits
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Sean Cross authored
The heap placer is important enough that we should just make it the default. Also, add a `USBSoC` that includes the required interrupt table, as this must be specified prior to calling `__init__()`. Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross authored
Use the memory array to find the address for the sram bank. Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross authored
Allow the user to specify a CPU. Signed-off-by: Sean Cross <sean@xobs.io>
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- 12 Sep, 2019 1 commit
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Florent Kermarrec authored
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- 11 Sep, 2019 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 10 Sep, 2019 1 commit
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Antti Lukats authored
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- 09 Sep, 2019 1 commit
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Florent Kermarrec authored
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- 03 Sep, 2019 1 commit
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Florent Kermarrec authored
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- 02 Sep, 2019 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Sean Cross authored
This adds the Fomu target back in. The default BaseSoC supports various USB methods, and will be updated as more become available. The debug bridge may optionally be added. Signed-off-by: Sean Cross <sean@xobs.io>
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- 01 Sep, 2019 2 commits
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Florent Kermarrec authored
targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
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Rohit Singh authored
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- 27 Aug, 2019 1 commit
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Florent Kermarrec authored
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- 26 Aug, 2019 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 22 Aug, 2019 1 commit
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Arnaud Durand authored
The system clock was driven directly while it should be driven by the PLL.
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- 11 Aug, 2019 1 commit
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DurandA authored
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- 09 Aug, 2019 4 commits
- 07 Aug, 2019 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
- use 1e9/freq for default_clk_period - add default serial on tinyfpga_bx - use S6PLL on minispartan6 - add SPIFlash pins on versa_ecp5
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- 12 Jul, 2019 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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