- 23 Jan, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 22 Jan, 2020 7 commits
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Florent Kermarrec authored
Tested with: ./colorlight_5a_75b.py --cpu-type=picorv32 --uart-name=crossover --with-etherbone --csr-csv=csr.csv Load with following script: #!/usr/bin/env python3 # Load --------------------------------------------------------------------------------------------- def load(): import os f = open("openocd.cfg", "w") f.write( """ interface ftdi ftdi_vid_pid 0x0403 0x6011 ftdi_channel 0 ftdi_layout_init 0x0098 0x008b reset_config none adapter_khz 25000 jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043 """) f.close() os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"") exit() if __name__ == "__main__": load() Then start lxserver: lxserver --udp And run following script: #!/usr/bin/env python3 import sys from litex import RemoteClient wb = RemoteClient() wb.open() # # # while True: if wb.regs.uart_xover_rxempty.read() == 0: print(chr(wb.regs.uart_xover_rxtx.read()), end="") sys.stdout.flush() # # # wb.close()
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 21 Jan, 2020 1 commit
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Florent Kermarrec authored
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- 18 Jan, 2020 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 17 Jan, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 16 Jan, 2020 6 commits
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Tim 'mithro' Ansell authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
Add Mimas A7 board support
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Florent Kermarrec authored
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
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Florent Kermarrec authored
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- 15 Jan, 2020 3 commits
- 13 Jan, 2020 6 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
ADD: KX2 and DDR3 support
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Florent Kermarrec authored
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Florent Kermarrec authored
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Mark authored
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- 11 Jan, 2020 1 commit
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Florent Kermarrec authored
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- 10 Jan, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 09 Jan, 2020 7 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
targets/de10lite: use external clock for sys directly
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Marcin Sloniewski authored
At the start output of the pll is not stabilized, which caused malfunctions when used for sys clock domain. Use AsyncResetSynchronizer to start clock domains on pll locked signal.
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Gabriel Somlo authored
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