- 13 Jan, 2020 1 commit
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Florent Kermarrec authored
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- 11 Jan, 2020 1 commit
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Florent Kermarrec authored
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- 10 Jan, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 09 Jan, 2020 8 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
targets/de10lite: use external clock for sys directly
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Marcin Sloniewski authored
At the start output of the pll is not stabilized, which caused malfunctions when used for sys clock domain. Use AsyncResetSynchronizer to start clock domains on pll locked signal.
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Gabriel Somlo authored
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Florent Kermarrec authored
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- 08 Jan, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 07 Jan, 2020 5 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
add the Hackaday Supercon ECP5 badge
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enjoy-digital authored
Update ecp5_evn.py
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Arnaud Durand authored
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- 06 Jan, 2020 1 commit
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Drew Fustini authored
Add the Hackaday Supercon 2019 badge which has an ECP5 FPGA: https://hackaday.io/project/167255-2019-hackaday-superconference-badge These changes are from Michael Welling's fork: https://github.com/mwelling/linux-on-litex-vexriscv During Supercon, we trying two approaches: - use the built-in 16MB QSPI SRAM - use add-on cartiridge with 32MB SDRAM by Jacob Creedon We were not able to get the QSPI SRAM working so I've removed those changes, and I have just added the changes that are needed to boot Linux with the 32MB SDRAM. Thanks to Jacob Creedon, Greg Davill and Tim Ansell who helped debug. KiCad design files for the SDRAM cartridge are available at: https://github.com/jcreedon/dram-cart/ The SDRAM cartridge PCB is shared at: https://oshpark.com/shared_projects/IQSl2lid More information in this blog post: https://blog.oshpark.com/2019/12/20/ The Hackaday Supercon badge PCB design is here: https://github.com/Spritetm/hadbadge2019_pcb
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- 03 Jan, 2020 1 commit
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Tim Ansell authored
Updating the templates for Fomu.
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- 02 Jan, 2020 1 commit
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Tim 'mithro' Ansell authored
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- 31 Dec, 2019 7 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
Adding initial support for Saanlima's Pipistrello LX45 board
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Florent Kermarrec authored
targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer)
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Florent Kermarrec authored
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enjoy-digital authored
Update de10lite platform
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- 30 Dec, 2019 9 commits
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msloniewski authored
Add VideoSoC build option, based on Frank Buss example.
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msloniewski authored
Use PLL to generate clock for both sys clock domain and clock domain for sdram. Additionally set up clock domain for VGA periph.
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msloniewski authored
Use single image with memory initialization to make more space for SoC ROM sector.
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msloniewski authored
V10 and W10 pins were used in UART periph, causing error when gpio_0 were requested.
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Tim 'mithro' Ansell authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Giammarco Zacheo authored
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- 14 Dec, 2019 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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