Commit 48476be9 authored by Florent Kermarrec's avatar Florent Kermarrec
Browse files

aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address

parent 71840325
...@@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM): ...@@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.mem_map["csr"]) lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma
......
...@@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM): ...@@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.mem_map["csr"]) lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma
......
...@@ -105,7 +105,7 @@ class TagusSoC(SoCSDRAM): ...@@ -105,7 +105,7 @@ class TagusSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.mem_map["csr"]) lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma
......
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