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Timothy Pearson
litex-boards
Commits
48476be9
Commit
48476be9
authored
4 years ago
by
Florent Kermarrec
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aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address
parent
71840325
Changes
3
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3 changed files
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3 additions
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3 deletions
+3
-3
litex_boards/partner/targets/aller.py
litex_boards/partner/targets/aller.py
+1
-1
litex_boards/partner/targets/nereid.py
litex_boards/partner/targets/nereid.py
+1
-1
litex_boards/partner/targets/tagus.py
litex_boards/partner/targets/tagus.py
+1
-1
No files found.
litex_boards/partner/targets/aller.py
View file @
48476be9
...
@@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM):
...
@@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM):
# pcie wishbone bridge
# pcie wishbone bridge
self
.
submodules
.
pcie_wishbone
=
LitePCIeWishboneBridge
(
self
.
pcie_endpoint
,
self
.
submodules
.
pcie_wishbone
=
LitePCIeWishboneBridge
(
self
.
pcie_endpoint
,
lambda
a
:
1
,
shadow_base
=
self
.
mem_map
[
"csr"
])
lambda
a
:
1
,
base_address
=
self
.
mem_map
[
"csr"
])
self
.
add_wb_master
(
self
.
pcie_wishbone
.
wishbone
)
self
.
add_wb_master
(
self
.
pcie_wishbone
.
wishbone
)
# pcie dma
# pcie dma
...
...
This diff is collapsed.
Click to expand it.
litex_boards/partner/targets/nereid.py
View file @
48476be9
...
@@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM):
...
@@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM):
# pcie wishbone bridge
# pcie wishbone bridge
self
.
submodules
.
pcie_wishbone
=
LitePCIeWishboneBridge
(
self
.
pcie_endpoint
,
self
.
submodules
.
pcie_wishbone
=
LitePCIeWishboneBridge
(
self
.
pcie_endpoint
,
lambda
a
:
1
,
shadow_base
=
self
.
mem_map
[
"csr"
])
lambda
a
:
1
,
base_address
=
self
.
mem_map
[
"csr"
])
self
.
add_wb_master
(
self
.
pcie_wishbone
.
wishbone
)
self
.
add_wb_master
(
self
.
pcie_wishbone
.
wishbone
)
# pcie dma
# pcie dma
...
...
This diff is collapsed.
Click to expand it.
litex_boards/partner/targets/tagus.py
View file @
48476be9
...
@@ -105,7 +105,7 @@ class TagusSoC(SoCSDRAM):
...
@@ -105,7 +105,7 @@ class TagusSoC(SoCSDRAM):
# pcie wishbone bridge
# pcie wishbone bridge
self
.
submodules
.
pcie_wishbone
=
LitePCIeWishboneBridge
(
self
.
pcie_endpoint
,
self
.
submodules
.
pcie_wishbone
=
LitePCIeWishboneBridge
(
self
.
pcie_endpoint
,
lambda
a
:
1
,
shadow_base
=
self
.
mem_map
[
"csr"
])
lambda
a
:
1
,
base_address
=
self
.
mem_map
[
"csr"
])
self
.
add_wb_master
(
self
.
pcie_wishbone
.
wishbone
)
self
.
add_wb_master
(
self
.
pcie_wishbone
.
wishbone
)
# pcie dma
# pcie dma
...
...
This diff is collapsed.
Click to expand it.
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