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Timothy Pearson
litex-boards
Commits
15371895
Unverified
Commit
15371895
authored
4 years ago
by
enjoy-digital
Committed by
GitHub
4 years ago
Browse files
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Merge pull request #83 from madscientist159/master
Fix Microwatt on Versa board
parents
9b45ec0f
90092164
Changes
2
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Showing
2 changed files
with
14 additions
and
7 deletions
+14
-7
litex_boards/platforms/versa_ecp5.py
litex_boards/platforms/versa_ecp5.py
+2
-2
litex_boards/targets/versa_ecp5.py
litex_boards/targets/versa_ecp5.py
+12
-5
No files found.
litex_boards/platforms/versa_ecp5.py
View file @
15371895
...
...
@@ -221,8 +221,8 @@ class Platform(LatticePlatform):
default_clk_name
=
"clk100"
default_clk_period
=
1e9
/
100e6
def
__init__
(
self
,
**
kwargs
):
LatticePlatform
.
__init__
(
self
,
"LFE5UM5G-45F-8BG381C"
,
_io
,
_connectors
,
**
kwargs
)
def
__init__
(
self
,
device
=
"LFE5UM5G-45F-8BG381C"
,
**
kwargs
):
LatticePlatform
.
__init__
(
self
,
device
,
_io
,
_connectors
,
**
kwargs
)
def
create_programmer
(
self
):
return
OpenOCDJTAGProgrammer
(
"openocd_versa_ecp5.cfg"
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/versa_ecp5.py
View file @
15371895
...
...
@@ -73,8 +73,14 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCCore
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
75e6
),
with_ethernet
=
False
,
toolchain
=
"trellis"
,
**
kwargs
):
platform
=
versa_ecp5
.
Platform
(
toolchain
=
toolchain
)
def
__init__
(
self
,
sys_clk_freq
=
int
(
75e6
),
device
=
"LFE5UM5G-45F-8BG381C"
,
with_ethernet
=
False
,
toolchain
=
"trellis"
,
**
kwargs
):
platform
=
versa_ecp5
.
Platform
(
toolchain
=
toolchain
,
device
=
device
)
# Fix ROM size for Microwatt
if
with_ethernet
:
kwargs
[
"integrated_rom_size"
]
=
0xb000
else
:
kwargs
[
"integrated_rom_size"
]
=
0x9000
# SoCCore -----------------------------------------_----------------------------------------
SoCCore
.
__init__
(
self
,
platform
,
clk_freq
=
sys_clk_freq
,
**
kwargs
)
...
...
@@ -123,11 +129,12 @@ def main():
builder_args
(
parser
)
soc_sdram_args
(
parser
)
trellis_args
(
parser
)
parser
.
add_argument
(
"--sys-clk-freq"
,
default
=
75e6
,
help
=
"System clock frequency (default=75MHz)"
)
parser
.
add_argument
(
"--with-ethernet"
,
action
=
"store_true"
,
help
=
"Enable Ethernet support"
)
parser
.
add_argument
(
"--sys-clk-freq"
,
default
=
75e6
,
help
=
"System clock frequency (default=75MHz)"
)
parser
.
add_argument
(
"--device"
,
default
=
"LFE5UM5G-45F-8BG381C"
,
help
=
"ECP5 device (default=LFE5UM5G-45F-8BG381C)"
)
parser
.
add_argument
(
"--with-ethernet"
,
action
=
"store_true"
,
help
=
"Enable Ethernet support"
)
args
=
parser
.
parse_args
()
soc
=
BaseSoC
(
sys_clk_freq
=
int
(
float
(
args
.
sys_clk_freq
)),
with_ethernet
=
args
.
with_ethernet
,
toolchain
=
args
.
toolchain
,
**
soc_sdram_argdict
(
args
))
soc
=
BaseSoC
(
sys_clk_freq
=
int
(
float
(
args
.
sys_clk_freq
)),
device
=
args
.
device
,
with_ethernet
=
args
.
with_ethernet
,
toolchain
=
args
.
toolchain
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder_kargs
=
trellis_argdict
(
args
)
if
args
.
toolchain
==
"trellis"
else
{}
builder
.
build
(
**
builder_kargs
,
run
=
args
.
build
)
...
...
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