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Timothy Pearson
litex-boards
Commits
9b45ec0f
Commit
9b45ec0f
authored
4 years ago
by
Florent Kermarrec
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de10lite: simplify vga terminal.
parent
85cac7ab
Changes
2
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2 changed files
with
17 additions
and
30 deletions
+17
-30
litex_boards/platforms/de10lite.py
litex_boards/platforms/de10lite.py
+1
-1
litex_boards/targets/de10lite.py
litex_boards/targets/de10lite.py
+16
-29
No files found.
litex_boards/platforms/de10lite.py
View file @
9b45ec0f
...
...
@@ -66,7 +66,7 @@ _io = [
IOStandard
(
"3.3-V LVTTL"
)
),
(
"vga
_out
"
,
0
,
(
"vga"
,
0
,
Subsignal
(
"hsync_n"
,
Pins
(
"N3"
)),
Subsignal
(
"vsync_n"
,
Pins
(
"N1"
)),
Subsignal
(
"r"
,
Pins
(
"AA1 V1 Y2 Y1"
)),
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/de10lite.py
View file @
9b45ec0f
...
...
@@ -14,6 +14,7 @@ from litex.build.io import DDROutput
from
litex_boards.platforms
import
de10lite
from
litex.soc.cores.clock
import
Max10PLL
from
litex.soc.integration.soc
import
SoCRegion
from
litex.soc.integration.soc_core
import
*
from
litex.soc.integration.soc_sdram
import
*
from
litex.soc.integration.builder
import
*
...
...
@@ -50,7 +51,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCCore
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
50e6
),
**
kwargs
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
50e6
),
with_vga
=
False
,
**
kwargs
):
platform
=
de10lite
.
Platform
()
# SoCCore ----------------------------------------------------------------------------------
...
...
@@ -72,38 +73,25 @@ class BaseSoC(SoCCore):
l2_cache_reverse
=
True
)
# VGA Terminal -----------------------------------------------------------------------------
if
with_vga
:
self
.
submodules
.
terminal
=
terminal
=
Terminal
()
self
.
bus
.
add_slave
(
"terminal"
,
self
.
terminal
.
bus
,
region
=
SoCRegion
(
origin
=
0x30000000
,
size
=
0x10000
))
vga_pads
=
platform
.
request
(
"vga"
)
self
.
comb
+=
[
vga_pads
.
vsync_n
.
eq
(
terminal
.
vsync
),
vga_pads
.
hsync_n
.
eq
(
terminal
.
hsync
),
vga_pads
.
r
.
eq
(
terminal
.
red
[
4
:
8
]),
vga_pads
.
g
.
eq
(
terminal
.
green
[
4
:
8
]),
vga_pads
.
b
.
eq
(
terminal
.
blue
[
4
:
8
])
]
# Leds -------------------------------------------------------------------------------------
self
.
submodules
.
leds
=
LedChaser
(
pads
=
Cat
(
*
[
platform
.
request
(
"user_led"
,
i
)
for
i
in
range
(
10
)]),
sys_clk_freq
=
sys_clk_freq
)
self
.
add_csr
(
"leds"
)
# VGASoC -------------------------------------------------------------------------------------------
class
VGASoC
(
BaseSoC
):
mem_map
=
{
"terminal"
:
0x30000000
,
}
mem_map
.
update
(
BaseSoC
.
mem_map
)
def
__init__
(
self
,
**
kwargs
):
BaseSoC
.
__init__
(
self
,
**
kwargs
)
# create VGA terminal
self
.
submodules
.
terminal
=
terminal
=
Terminal
()
self
.
add_wb_slave
(
self
.
mem_map
[
"terminal"
],
self
.
terminal
.
bus
)
self
.
add_memory_region
(
"terminal"
,
self
.
mem_map
[
"terminal"
],
0x10000
)
# connect VGA pins
vga
=
self
.
platform
.
request
(
'vga_out'
,
0
)
self
.
comb
+=
[
vga
.
vsync_n
.
eq
(
terminal
.
vsync
),
vga
.
hsync_n
.
eq
(
terminal
.
hsync
),
vga
.
r
.
eq
(
terminal
.
red
[
4
:
8
]),
vga
.
g
.
eq
(
terminal
.
green
[
4
:
8
]),
vga
.
b
.
eq
(
terminal
.
blue
[
4
:
8
])
]
# Build --------------------------------------------------------------------------------------------
def
main
():
...
...
@@ -115,8 +103,7 @@ def main():
parser
.
add_argument
(
"--with-vga"
,
action
=
"store_true"
,
help
=
"Enable VGA support"
)
args
=
parser
.
parse_args
()
cls
=
VGASoC
if
args
.
with_vga
else
BaseSoC
soc
=
cls
(
**
soc_sdram_argdict
(
args
))
soc
=
BaseSoC
(
with_vga
=
args
.
with_vga
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder
.
build
(
run
=
args
.
build
)
...
...
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