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Timothy Pearson
litex-boards
Commits
04f6d446
Commit
04f6d446
authored
4 years ago
by
Florent Kermarrec
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versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt.
parent
15371895
Changes
2
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2 changed files
with
15 additions
and
12 deletions
+15
-12
litex_boards/platforms/versa_ecp5.py
litex_boards/platforms/versa_ecp5.py
+3
-2
litex_boards/targets/versa_ecp5.py
litex_boards/targets/versa_ecp5.py
+12
-10
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litex_boards/platforms/versa_ecp5.py
View file @
04f6d446
...
...
@@ -221,8 +221,9 @@ class Platform(LatticePlatform):
default_clk_name
=
"clk100"
default_clk_period
=
1e9
/
100e6
def
__init__
(
self
,
device
=
"LFE5UM5G-45F-8BG381C"
,
**
kwargs
):
LatticePlatform
.
__init__
(
self
,
device
,
_io
,
_connectors
,
**
kwargs
)
def
__init__
(
self
,
device
=
"LFE5UM5G"
,
**
kwargs
):
assert
device
in
[
"LFE5UM5G"
,
"LFE5UM"
]
LatticePlatform
.
__init__
(
self
,
device
+
"-45F-8BG381C"
,
_io
,
_connectors
,
**
kwargs
)
def
create_programmer
(
self
):
return
OpenOCDJTAGProgrammer
(
"openocd_versa_ecp5.cfg"
)
...
...
This diff is collapsed.
Click to expand it.
litex_boards/targets/versa_ecp5.py
View file @
04f6d446
...
...
@@ -73,14 +73,12 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCCore
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
75e6
),
device
=
"LFE5UM5G
-45F-8BG381C
"
,
with_ethernet
=
False
,
toolchain
=
"trellis"
,
**
kwargs
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
75e6
),
device
=
"LFE5UM5G"
,
with_ethernet
=
False
,
toolchain
=
"trellis"
,
**
kwargs
):
platform
=
versa_ecp5
.
Platform
(
toolchain
=
toolchain
,
device
=
device
)
# Fix ROM size for Microwatt
if
with_ethernet
:
kwargs
[
"integrated_rom_size"
]
=
0xb000
else
:
kwargs
[
"integrated_rom_size"
]
=
0x9000
# FIXME: adapt integrated rom size for Microwatt
if
kwargs
.
get
(
"cpu_type"
,
None
)
==
"microwatt"
:
kwargs
[
"integrated_rom_size"
]
=
0xb000
if
with_ethernet
else
0x9000
# SoCCore -----------------------------------------_----------------------------------------
SoCCore
.
__init__
(
self
,
platform
,
clk_freq
=
sys_clk_freq
,
**
kwargs
)
...
...
@@ -129,12 +127,16 @@ def main():
builder_args
(
parser
)
soc_sdram_args
(
parser
)
trellis_args
(
parser
)
parser
.
add_argument
(
"--sys-clk-freq"
,
default
=
75e6
,
help
=
"System clock frequency (default=75MHz)"
)
parser
.
add_argument
(
"--device"
,
default
=
"LFE5UM5G
-45F-8BG381C
"
,
help
=
"ECP5 device (default
=
LFE5UM
5G-45F-8BG381C
)"
)
parser
.
add_argument
(
"--with-ethernet"
,
action
=
"store_true"
,
help
=
"Enable Ethernet support"
)
parser
.
add_argument
(
"--sys-clk-freq"
,
default
=
75e6
,
help
=
"System clock frequency (default=75MHz)"
)
parser
.
add_argument
(
"--device"
,
default
=
"LFE5UM5G"
,
help
=
"ECP5 device
(LFE5UM5G
(default
) or
LFE5UM)"
)
parser
.
add_argument
(
"--with-ethernet"
,
action
=
"store_true"
,
help
=
"Enable Ethernet support"
)
args
=
parser
.
parse_args
()
soc
=
BaseSoC
(
sys_clk_freq
=
int
(
float
(
args
.
sys_clk_freq
)),
device
=
args
.
device
,
with_ethernet
=
args
.
with_ethernet
,
toolchain
=
args
.
toolchain
,
**
soc_sdram_argdict
(
args
))
soc
=
BaseSoC
(
sys_clk_freq
=
int
(
float
(
args
.
sys_clk_freq
)),
device
=
args
.
device
,
with_ethernet
=
args
.
with_ethernet
,
toolchain
=
args
.
toolchain
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder_kargs
=
trellis_argdict
(
args
)
if
args
.
toolchain
==
"trellis"
else
{}
builder
.
build
(
**
builder_kargs
,
run
=
args
.
build
)
...
...
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