genesys2.py 4.24 KB
Newer Older
1 2
#!/usr/bin/env python3

Florent Kermarrec's avatar
Florent Kermarrec committed
3 4 5
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD

6 7 8 9
import argparse

from migen import *

10
from litex_boards.platforms import genesys2
11 12 13 14 15 16 17 18 19

from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *

from litedram.modules import MT41J256M16
from litedram.phy import s7ddrphy

from liteeth.phy.s7rgmii import LiteEthPHYRGMII
Florent Kermarrec's avatar
Florent Kermarrec committed
20
from liteeth.mac import LiteEthMAC
21 22 23 24 25

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
    def __init__(self, platform, sys_clk_freq):
26 27
        self.clock_domains.cd_sys    = ClockDomain()
        self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
28 29 30 31 32 33 34
        self.clock_domains.cd_clk200 = ClockDomain()

        # # #

        self.submodules.pll = pll = S7MMCM(speedgrade=-2)
        self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
        pll.register_clkin(platform.request("clk200"), 200e6)
35 36
        pll.create_clkout(self.cd_sys,    sys_clk_freq)
        pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
37 38 39 40 41 42 43
        pll.create_clkout(self.cd_clk200, 200e6)

        self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)

# BaseSoC ------------------------------------------------------------------------------------------

class BaseSoC(SoCSDRAM):
44
    def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
45
        platform = genesys2.Platform()
46 47

        # SoCSDRAM ---------------------------------------------------------------------------------
48
        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
49 50 51
            integrated_rom_size  = integrated_rom_size,
            integrated_sram_size = 0x8000,
            **kwargs)
52

53
        # CRG --------------------------------------------------------------------------------------
54 55
        self.submodules.crg = _CRG(platform, sys_clk_freq)

56 57 58 59 60 61 62 63 64 65 66
        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                memtype      = "DDR3",
                nphases      = 4,
                sys_clk_freq = sys_clk_freq)
            self.add_csr("ddrphy")
            sdram_module = MT41J256M16(self.clk_freq, "1:4")
            self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)

# EthernetSoC --------------------------------------------------------------------------------------
67 68 69

class EthernetSoC(BaseSoC):
    mem_map = {
70
        "ethmac": 0xb0000000,
71 72 73 74
    }
    mem_map.update(BaseSoC.mem_map)

    def __init__(self, **kwargs):
75
        BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
76 77 78 79 80 81

        self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                 self.platform.request("eth"))
        self.add_csr("ethphy")
        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
            interface="wishbone", endianness=self.cpu.endianness)
Florent Kermarrec's avatar
Florent Kermarrec committed
82
        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
83
        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
        self.add_csr("ethmac")
        self.add_interrupt("ethmac")

        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
        self.platform.add_false_path_constraints(
            self.crg.cd_sys.clk,
            self.ethphy.crg.cd_eth_rx.clk,
            self.ethphy.crg.cd_eth_tx.clk)

# Build --------------------------------------------------------------------------------------------

def main():
    parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
    builder_args(parser)
    soc_sdram_args(parser)
    parser.add_argument("--with-ethernet", action="store_true",
                        help="enable Ethernet support")
    args = parser.parse_args()

    cls = EthernetSoC if args.with_ethernet else BaseSoC
    soc = cls(**soc_sdram_argdict(args))
    builder = Builder(soc, **builder_argdict(args))
    builder.build()


if __name__ == "__main__":
    main()