Commit 4213c75e authored by Florent Kermarrec's avatar Florent Kermarrec

init repo with litex official boards

parents
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/ / (_) /____ | |/_/___/ _ )___ ___ ________/ /__
/ /__/ / __/ -_)> </___/ _ / _ \/ _ `/ __/ _ (_-<
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LiteX boards files
Copyright 2012-2019 / LiteX-Hub community
[> Intro
--------
Supported boards files (platforms/targets) for LiteX.
Official:
---------
Platforms / Targets actively tested and included in the CI system.
Partner:
-------
Platforms / Targets supported by other groups/partners.
Community:
----------
Platforms / Targets supported by the community in a "best effort" manner.
# This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
("clk200", 0,
Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
),
("clk156", 0,
Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
),
("serial", 0,
Subsignal("cts", Pins("V19")),
Subsignal("rts", Pins("W19")),
Subsignal("tx", Pins("U19")),
Subsignal("rx", Pins("T19")),
IOStandard("LVCMOS18")
),
("eth_clocks", 0,
Subsignal("tx", Pins("U22")),
Subsignal("rx", Pins("U21")),
IOStandard("LVCMOS18")
),
("eth", 0,
Subsignal("rx_ctl", Pins("U14")),
Subsignal("rx_data", Pins("U17 V17 V16 V14")),
Subsignal("tx_ctl", Pins("T15")),
Subsignal("tx_data", Pins("U16 U15 T18 T17")),
Subsignal("rst_n", Pins("V18")),
Subsignal("mdc", Pins("W18")),
Subsignal("mdio", Pins("T14")),
IOStandard("LVCMOS18"), Misc("SLEW=FAST"), Drive(16)
),
("ddram", 0,
Subsignal("a", Pins(
"M4 J3 J1 L4 K5 M7 K1 M6",
"H1 K3 N7 L5 L7 N6 L3 K2"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("N1 M1 H2"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P1"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("T4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R1"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
Subsignal("dm", Pins("AC6 AC4 AA3 U7 G1 F3 G5 H9"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7",
"AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4",
"AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1",
"Y3 W3 W6 V6 W4 W5 W1 V1",
"G2 D1 E1 E2 F2 A2 A3 C2",
"C3 D3 A4 B4 C4 D4 D5 E5",
"F4 G4 K6 K7 K8 L8 J5 J6",
"G6 H6 F7 F8 G8 H8 D6 E6"),
IOStandard("SSTL15")),
Subsignal("dqs_p", Pins("V8 AD5 AD1 V3 C1 B5 J4 H7"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("W8 AE5 AE1 V2 B1 A5 H4 G7"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("M2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("L2"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("P4"), IOStandard("SSTL15")),
Subsignal("odt", Pins("R2"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15"))
),
("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
("gtp_refclk", 0,
Subsignal("p", Pins("AA13")),
Subsignal("n", Pins("AB13"))
),
("sfp", 0,
Subsignal("txp", Pins("AC10")),
Subsignal("txn", Pins("AD10")),
Subsignal("rxp", Pins("AC12")),
Subsignal("rxn", Pins("AD12")),
),
("sfp_mgt_clk_sel0", 0, Pins("B26"), IOStandard("LVCMOS25")),
("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"CLK0_M2C_N": "C19",
"CLK0_M2C_P": "D19",
"CLK1_M2C_N": "H22",
"CLK1_M2C_P": "H21",
"LA00_CC_N": "C18",
"LA00_CC_P": "D18",
"LA01_CC_N": "E18",
"LA01_CC_P": "E17",
"LA02_N": "H15",
"LA02_P": "H14",
"LA03_N": "F17",
"LA03_P": "G17",
"LA04_N": "F19",
"LA04_P": "F18",
"LA05_N": "F15",
"LA05_P": "G15",
"LA06_N": "F20",
"LA06_P": "G19",
"LA07_N": "G16",
"LA07_P": "H16",
"LA08_N": "B17",
"LA08_P": "C17",
"LA09_N": "D16",
"LA09_P": "E16",
"LA10_N": "A18",
"LA10_P": "A17",
"LA11_N": "A19",
"LA11_P": "B19",
"LA12_N": "D20",
"LA12_P": "E20",
"LA13_N": "A20",
"LA13_P": "B20",
"LA14_N": "B21",
"LA14_P": "C21",
"LA15_N": "A22",
"LA15_P": "B22",
"LA16_N": "D21",
"LA16_P": "E21",
"LA17_CC_N": "J21",
"LA17_CC_P": "K21",
"LA18_CC_N": "G21",
"LA18_CC_P": "G20",
"LA19_N": "L14",
"LA19_P": "M14",
"LA20_N": "M17",
"LA20_P": "M16",
"LA21_N": "H19",
"LA21_P": "J19",
"LA22_N": "L18",
"LA22_P": "L17",
"LA23_N": "J20",
"LA23_P": "K20",
"LA24_N": "H18",
"LA24_P": "J18",
"LA25_N": "F22",
"LA25_P": "G22",
"LA26_N": "H24",
"LA26_P": "J24",
"LA27_N": "E23",
"LA27_P": "F23",
"LA28_N": "K23",
"LA28_P": "K22",
"LA29_N": "F24",
"LA29_P": "G24",
"LA30_N": "D25",
"LA30_P": "E25",
"LA31_N": "D26",
"LA31_P": "E26",
"LA32_N": "G26",
"LA32_P": "H26",
"LA33_N": "F25",
"LA33_P": "G25",
"PRSNT_M2C_L": "N16",
"PWR_GOOD_FLASH_RST_B": "P15"}
),
("XADC", {
"GPIO0": "H17",
"GPIO1": "E22",
"GPIO2": "K18",
"GPIO3": "L19",
"VAUX0_N": "J16",
"VAUX0_P": "K15",
"VAUX8_N": "J15",
"VAUX8_P": "J14",
}
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 6.4
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
except ConstraintError:
pass
# This file is Copyright (c) 2015 Yann Sionneau <yann@sionneau.net>
# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
# This file is Copyright (c) 2018 Caleb Jamison <cbjamo@gmail.com>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("G6")),
Subsignal("g", Pins("F6")),
Subsignal("b", Pins("E1")),
IOStandard("LVCMOS33"),
),
("rgb_led", 1,
Subsignal("r", Pins("G3")),
Subsignal("g", Pins("J4")),
Subsignal("b", Pins("G4")),
IOStandard("LVCMOS33"),
),
("rgb_led", 2,
Subsignal("r", Pins("J3")),
Subsignal("g", Pins("J2")),
Subsignal("b", Pins("H4")),
IOStandard("LVCMOS33"),
),
("rgb_led", 3,
Subsignal("r", Pins("K1")),
Subsignal("g", Pins("H6")),
Subsignal("b", Pins("K2")),
IOStandard("LVCMOS33"),
),
("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("D10")),
Subsignal("rx", Pins("A9")),
IOStandard("LVCMOS33")
),
("spi", 0,
Subsignal("clk", Pins("F1")),
Subsignal("cs_n", Pins("C1")),
Subsignal("mosi", Pins("H1")),
Subsignal("miso", Pins("G1")),
IOStandard("LVCMOS33"),
),
("i2c", 0,
Subsignal("scl", Pins("L18")),
Subsignal("sda", Pins("M18")),
Subsignal("scl_pup", Pins("A14")),
Subsignal("sda_pup", Pins("A13")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L13")),
Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
IOStandard("LVCMOS33")
),
("spiflash", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L13")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),
Subsignal("hold", Pins("M14")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"R2 M6 N4 T1 N6 R7 V6 U7",
"R8 V7 R6 U6 T6 T8"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("P3"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("M4"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("P5"), IOStandard("SSTL135")),
Subsignal("cs_n", Pins("U8"), IOStandard("SSTL135")),
Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL135")),
Subsignal("dq", Pins(
"K5 L3 K3 L6 M3 M1 L4 M2",
"V4 T5 U4 V5 V1 T3 U3 R3"),
IOStandard("SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL135")),
Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("N5"), IOStandard("SSTL135")),
Subsignal("odt", Pins("R5"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("K6"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
("eth_clocks", 0,
Subsignal("tx", Pins("H16")),
Subsignal("rx", Pins("F15")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("C16")),
Subsignal("mdio", Pins("K13")),
Subsignal("mdc", Pins("F16")),
Subsignal("rx_dv", Pins("G16")),
Subsignal("rx_er", Pins("C17")),
Subsignal("rx_data", Pins("D18 E17 E18 G17")),
Subsignal("tx_en", Pins("H15")),
Subsignal("tx_data", Pins("H14 J14 J13 H17")),
Subsignal("col", Pins("D17")),
Subsignal("crs", Pins("G14")),
IOStandard("LVCMOS33"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("pmoda", "G13 B11 A11 D12 D13 B18 A18 K16"),
("pmodb", "E15 E16 D15 C15 J17 J18 K15 J15"),
("pmodc", "U12 V12 V10 V11 U14 V14 T13 U13"),
("pmodd", "D4 D3 F4 F3 E2 D2 H2 G2"),
("ck_io", {
# Outer Digital Header
"ck_io0" : "V15",
"ck_io1" : "U16",
"ck_io2" : "P14",
"ck_io3" : "T11",
"ck_io4" : "R12",
"ck_io5" : "T14",
"ck_io6" : "T15",
"ck_io7" : "T16",
"ck_io8" : "N15",
"ck_io9" : "M16",
"ck_io10" : "V17",
"ck_io11" : "U18",
"ck_io12" : "R17",
"ck_io13" : "P17",
# Inner Digital Header
"ck_io26" : "U11",
"ck_io27" : "V16",
"ck_io28" : "M13",
"ck_io29" : "R10",
"ck_io30" : "R11",
"ck_io31" : "R13",
"ck_io32" : "R15",
"ck_io33" : "P15",
"ck_io34" : "R16",
"ck_io35" : "N16",
"ck_io36" : "N14",
"ck_io37" : "U17",
"ck_io38" : "T18",
"ck_io39" : "R18",
"ck_io40" : "P18",
"ck_io41" : "N17",
# Outer Analog Header as Digital IO
"ck_a0" : "F5",
"ck_a1" : "D8",
"ck_a2" : "C7",
"ck_a3" : "E7",
"ck_a4" : "D7",
"ck_a5" : "D5",
# Inner Analog Header as Digital IO
"ck_io20" : "B7",
"ck_io21" : "B6",
"ck_io22" : "E6",
"ck_io23" : "E5",
"ck_io24" : "A4",
"ck_io25" : "A3",
} ),
("XADC", {
# Outer Analog Header
"vaux4_n" : "C5",
"vaux4_p" : "C6",
"vaux5_n" : "A5",
"vaux5_p" : "A6",
"vaux6_n" : "B4",
"vaux6_p" : "C4",
"vaux7_n" : "A1",
"vaux7_p" : "B1",
"vaux15_n" : "B2",
"vaux15_p" : "B3",
"vaux0_n" : "C14",
"vaux0_p" : "D14",
# Inner Analog Header
"vaux12_n" : "B7",
"vaux12_p" : "B6",
"vaux13_n" : "E6",
"vaux13_p" : "E5",
"vaux14_n" : "A4",
"vaux14_p" : "A3",
# Power Measurements
"vsnsuv_n" : "B17",
"vsnsuv_p" : "B16",
"vsns5v0_n" : "B12",
"vsns5v0_p" : "C12",
"isns5v0_n" : "F14",
"isns5v0_n" : "F13",
"isns0v95_n" : "A16",
"isns0v95_n" : "A15",
} ),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self, variant="a7-35"):
device = {
"a7-35": "xc7a35ticsg324-1L",
"a7-100": "xc7a100tcsg324-1"
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.microsemi import MicrosemiPlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk50", 0, Pins("R1"), IOStandard("LVCMOS25")),
("clk50", 1, Pins("J3"), IOStandard("LVCMOS25")),
("rst_n", 0, Pins("F5"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("D6"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("D7"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("D8"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("D9"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("E13"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("E14"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("F17")),
Subsignal("rx", Pins("F16")),
IOStandard("LVCMOS33")
),
("spiflash4x", 0,
Subsignal("clk", Pins("J1")),
Subsignal("cs_n", Pins("H1")),
Subsignal("dq", Pins("F2 F1 M7 M8")),
IOStandard("LVCMOS25")
),
("spiflash", 0,
Subsignal("clk", Pins("J1")),
Subsignal("cs_n", Pins("H1")),
Subsignal("mosi", Pins("F2")),
Subsignal("miso", Pins("F1")),
Subsignal("wp", Pins("M7")),
Subsignal("hold", Pins("M8")),
IOStandard("LVCMOS25"),
),
("ddram", 0,
Subsignal("a", Pins(
"U5 U4 V4 W3 V5 W4 Y3 AA3",
"Y4 Y5 AA2 AB2 V6 W6 AB3"),
IOStandard("SSTL15II")),
Subsignal("ba", Pins("V7 Y6 U7"), IOStandard("SSTL15II")),
Subsignal("ras_n", Pins("AA6"), IOStandard("SSTL15II")),
Subsignal("cas_n", Pins("AA5"), IOStandard("SSTL15II")),
Subsignal("we_n", Pins("AB5"), IOStandard("SSTL15II")),
Subsignal("cs_n", Pins("W7"), IOStandard("SSTL15II")),
Subsignal("dm", Pins("Y9 R15"), IOStandard("SSTL15II")),
Subsignal("dq", Pins(
"T7 T8 U8 U9 R10 V9 V10 W9",
"V14 U14 R12 T11 U15 T13 U13 T15"),
IOStandard("SSTL15II")),
Subsignal("dqs_p", Pins("T10 R13"), IOStandard("SSTL15II")),
Subsignal("dqs_n", Pins("U10 T12"), IOStandard("SSTL15II")),
Subsignal("clk_p", Pins("V2"), IOStandard("SSTL15II")),
Subsignal("clk_n", Pins("W2"), IOStandard("SSTL15II")),
Subsignal("cke", Pins("W8"), IOStandard("SSTL15II")),
Subsignal("odt", Pins("AA7"), IOStandard("SSTL15II")),
Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15II")),
),
("eth_clocks", 0,
Subsignal("tx", Pins("J8")),
Subsignal("rx", Pins("K3")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("L8"), IOStandard("LVCMOS33")),
Subsignal("int_n", Pins("J4")),
Subsignal("mdio", Pins("H2")),
Subsignal("mdc", Pins("J2")),
Subsignal("rx_ctl", Pins("K5")),
Subsignal("rx_data", Pins("J9 K1 K6 K4")),
Subsignal("tx_ctl", Pins("L5")),
Subsignal("tx_data", Pins("K8 L1 L2 L3")),
IOStandard("LVCMOS25")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(MicrosemiPlatform):
default_clk_name = "clk50"
default_clk_period = 20.0
def __init__(self):
MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io)
# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),
("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")),
("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")),
("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("T8"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("B4"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("B5"), IOStandard("3.3-V LVTTL"))
),
("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")),
Subsignal("ba", Pins("M7 M6")),
Subsignal("cs_n", Pins("P6")),
Subsignal("cke", Pins("L7")),
Subsignal("ras_n", Pins("L2")),
Subsignal("cas_n", Pins("L1")),
Subsignal("we_n", Pins("C2")),
Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")),
Subsignal("dm", Pins("R6 T5")),
IOStandard("3.3-V LVTTL")
),
("epcs", 0,
Subsignal("data0", Pins("H2")),
Subsignal("dclk", Pins("H1")),
Subsignal("ncs0", Pins("D2")),
Subsignal("asd0", Pins("C1")),
IOStandard("3.3-V LVTTL")
),
("i2c", 0,
Subsignal("sclk", Pins("F2")),
Subsignal("sdat", Pins("F1")),
IOStandard("3.3-V LVTTL")
),
("g_sensor", 0,
Subsignal("cs_n", Pins("G5")),
Subsignal("int", Pins("M2")),
IOStandard("3.3-V LVTTL")
),
("adc", 0,