Commit e9d52234 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
parents 955c5038 09af7b44

Too many changes to show.

To preserve performance only 163 of 163+ files are displayed.
README for MIPS AU1XXX IDE driver - Released 2005-07-15
ABOUT
-----
This file describes the 'drivers/ide/mips/au1xxx-ide.c', related files and the
services they provide.
If you are short in patience and just want to know how to add your hard disc to
the white or black list, go to the 'ADD NEW HARD DISC TO WHITE OR BLACK LIST'
section.
LICENSE
-------
Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
This program is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free Software
Foundation; either version 2 of the License, or (at your option) any later
version.
THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc.,
675 Mass Ave, Cambridge, MA 02139, USA.
Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
Interface and Linux Device Driver" Application Note.
FILES, CONFIGS AND COMPATABILITY
--------------------------------
Two files are introduced:
a) 'include/asm-mips/mach-au1x00/au1xxx_ide.h'
containes : struct _auide_hwif
struct drive_list_entry dma_white_list
struct drive_list_entry dma_black_list
timing parameters for PIO mode 0/1/2/3/4
timing parameters for MWDMA 0/1/2
b) 'drivers/ide/mips/au1xxx-ide.c'
contains the functionality of the AU1XXX IDE driver
Four configs variables are introduced:
CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA - enable the PIO+DBDMA mode
CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA - enable the MWDMA mode
CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON - set Burstable FIFO in DBDMA
controler
CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ - maximum transfer size
per descriptor
If MWDMA is enabled and the connected hard disc is not on the white list, the
kernel switches to a "safe mwdma mode" at boot time. In this mode the IDE
performance is substantial slower then in full speed mwdma. In this case
please add your hard disc to the white list (follow instruction from 'ADD NEW
HARD DISC TO WHITE OR BLACK LIST' section).
SUPPORTED IDE MODES
-------------------
The AU1XXX IDE driver supported all PIO modes - PIO mode 0/1/2/3/4 - and all
MWDMA modes - MWDMA 0/1/2 -. There is no support for SWDMA and UDMA mode.
To change the PIO mode use the program hdparm with option -p, e.g.
'hdparm -p0 [device]' for PIO mode 0. To enable the MWDMA mode use the option
-X, e.g. 'hdparm -X32 [device]' for MWDMA mode 0.
PERFORMANCE CONFIGURATIONS
--------------------------
If the used system doesn't need USB support enable the following kernel configs:
CONFIG_IDE=y
CONFIG_BLK_DEV_IDE=y
CONFIG_IDE_GENERIC=y
CONFIG_BLK_DEV_IDEPCI=y
CONFIG_BLK_DEV_GENERIC=y
CONFIG_BLK_DEV_IDEDMA_PCI=y
CONFIG_IDEDMA_PCI_AUTO=y
CONFIG_BLK_DEV_IDE_AU1XXX=y
CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON=y
CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128
CONFIG_BLK_DEV_IDEDMA=y
CONFIG_IDEDMA_AUTO=y
If the used system need the USB support enable the following kernel configs for
high IDE to USB throughput.
CONFIG_BLK_DEV_IDEDISK=y
CONFIG_IDE_GENERIC=y
CONFIG_BLK_DEV_IDEPCI=y
CONFIG_BLK_DEV_GENERIC=y
CONFIG_BLK_DEV_IDEDMA_PCI=y
CONFIG_IDEDMA_PCI_AUTO=y
CONFIG_BLK_DEV_IDE_AU1XXX=y
CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128
CONFIG_BLK_DEV_IDEDMA=y
CONFIG_IDEDMA_AUTO=y
ADD NEW HARD DISC TO WHITE OR BLACK LIST
----------------------------------------
Step 1 : detect the model name of your hard disc
a) connect your hard disc to the AU1XXX
b) boot your kernel and get the hard disc model.
Example boot log:
--snipped--
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx
Au1xxx IDE(builtin) configured for MWDMA2
Probing IDE interface ide0...
hda: Maxtor 6E040L0, ATA DISK drive
ide0 at 0xac800000-0xac800007,0xac8001c0 on irq 64
hda: max request size: 64KiB
hda: 80293248 sectors (41110 MB) w/2048KiB Cache, CHS=65535/16/63, (U)DMA
--snipped--
In this example 'Maxtor 6E040L0'.
Step 2 : edit 'include/asm-mips/mach-au1x00/au1xxx_ide.h'
Add your hard disc to the dma_white_list or dma_black_list structur.
Step 3 : Recompile the kernel
Enable MWDMA support in the kernel configuration. Recompile the kernel and
reboot.
Step 4 : Tests
If you have add a hard disc to the white list, please run some stress tests
for verification.
ACKNOWLEDGMENTS
---------------
These drivers wouldn't have been done without the base of kernel 2.4.x AU1XXX
IDE driver from AMD.
Additional input also from:
Matthias Lenk <matthias.lenk@amd.com>
Happy hacking!
Enrico Walther <enrico.walther@amd.com>
......@@ -1643,7 +1643,7 @@ S: Maintained
MIPS
P: Ralf Baechle
M: ralf@linux-mips.org
W: http://oss.sgi.com/mips/mips-howto.html
W: http://www.linux-mips.org/
L: linux-mips@linux-mips.org
S: Maintained
......
......@@ -4,216 +4,147 @@ config MIPS
# Horrible source of confusion. Die, die, die ...
select EMBEDDED
# shouldn't it be per-subarchitecture?
config ARCH_MAY_HAVE_PC_FDC
bool
default y
mainmenu "Linux/MIPS Kernel Configuration"
source "init/Kconfig"
config SYS_SUPPORTS_32BIT_KERNEL
bool
config SYS_SUPPORTS_64BIT_KERNEL
bool
config CPU_SUPPORTS_32BIT_KERNEL
bool
config CPU_SUPPORTS_64BIT_KERNEL
bool
menu "Kernel type"
choice
prompt "Kernel code model"
help
You should only select this option if you have a workload that
actually benefits from 64-bit processing or if your machine has
large memory. You will only be presented a single option in this
menu if your system does not support both 32-bit and 64-bit kernels.
config 32BIT
bool "32-bit kernel"
depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
select TRAD_SIGNALS
help
Select this option if you want to build a 32-bit kernel.
config 64BIT
bool "64-bit kernel"
depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
help
Select this option if you want to build a 64-bit kernel.
endchoice
endmenu
menu "Machine selection"
config MACH_JAZZ
bool "Support for the Jazz family of machines"
select ARC
select ARC32
select GENERIC_ISA_DMA
select I8259
select ISA
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
help
This a family of machines based on the MIPS R4030 chipset which was
used by several vendors to build RISC/os and Windows NT workstations.
Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
Olivetti M700-10 workstations.
choice
prompt "System type"
default SGI_IP22
config ACER_PICA_61
bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
depends on MACH_JAZZ && EXPERIMENTAL
config MIPS_MTX1
bool "Support for 4G Systems MTX-1 board"
select DMA_NONCOHERENT
help
This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
kernel that runs on these, say Y here. For details about Linux on
the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
<http://www.linux-mips.org/>.
select HW_HAS_PCI
select SOC_AU1500
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_MAGNUM_4000
bool "Support for MIPS Magnum 4000"
depends on MACH_JAZZ
config MIPS_BOSPORUS
bool "AMD Alchemy Bosporus board"
select SOC_AU1500
select DMA_NONCOHERENT
help
This is a machine with a R4000 100 MHz CPU. To compile a Linux
kernel that runs on these, say Y here. For details about Linux on
the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
<http://www.linux-mips.org/>.
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config OLIVETTI_M700
bool "Support for Olivetti M700-10"
depends on MACH_JAZZ
config MIPS_PB1000
bool "AMD Alchemy PB1000 board"
select SOC_AU1000
select DMA_NONCOHERENT
help
This is a machine with a R4000 100 MHz CPU. To compile a Linux
kernel that runs on these, say Y here. For details about Linux on
the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
<http://www.linux-mips.org/>.
config MACH_VR41XX
bool "Support for NEC VR4100 series based machines"
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select HW_HAS_PCI
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config NEC_CMBVR4133
bool "Support for NEC CMB-VR4133"
depends on MACH_VR41XX
select CPU_VR41XX
config MIPS_PB1100
bool "AMD Alchemy PB1100 board"
select SOC_AU1100
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config ROCKHOPPER
bool "Support for Rockhopper baseboard"
depends on NEC_CMBVR4133
select I8259
select HAVE_STD_PC_SERIAL_PORT
config MIPS_PB1500
bool "AMD Alchemy PB1500 board"
select SOC_AU1500
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config CASIO_E55
bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
depends on MACH_VR41XX
select CPU_LITTLE_ENDIAN
config MIPS_PB1550
bool "AMD Alchemy PB1550 board"
select SOC_AU1550
select DMA_NONCOHERENT
select IRQ_CPU
select ISA
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config IBM_WORKPAD
bool "Support for IBM WorkPad z50"
depends on MACH_VR41XX
select CPU_LITTLE_ENDIAN
config MIPS_PB1200
bool "AMD Alchemy PB1200 board"
select SOC_AU1200
select DMA_NONCOHERENT
select IRQ_CPU
select ISA
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config TANBAC_TB022X
bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
depends on MACH_VR41XX
select CPU_LITTLE_ENDIAN
config MIPS_DB1000
bool "AMD Alchemy DB1000 board"
select SOC_AU1000
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
help
The TANBAC VR4131 multichip module(TB0225) and
the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
manufactured by TANBAC.
Please refer to <http://www.tanbac.co.jp/>
about VR4131 multichip module and VR4131DIMM.
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config TANBAC_TB0226
bool "Support for TANBAC Mbase(TB0226)"
depends on TANBAC_TB022X
select GPIO_VR41XX
help
The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC.
Please refer to <http://www.tanbac.co.jp/> about Mbase.
config TANBAC_TB0287
bool "Support for TANBAC Mini-ITX DIMM base(TB0287)"
depends on TANBAC_TB022X
help
The TANBAC Mini-ITX DIMM base(TB0287) is a MIPS-based platform manufactured by TANBAC.
Please refer to <http://www.tanbac.co.jp/> about Mini-ITX DIMM base.
config VICTOR_MPC30X
bool "Support for Victor MP-C303/304"
depends on MACH_VR41XX
select CPU_LITTLE_ENDIAN
config MIPS_DB1100
bool "AMD Alchemy DB1100 board"
select SOC_AU1100
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config ZAO_CAPCELLA
bool "Support for ZAO Networks Capcella"
depends on MACH_VR41XX
select CPU_LITTLE_ENDIAN
config MIPS_DB1500
bool "AMD Alchemy DB1500 board"
select SOC_AU1500
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config PCI_VR41XX
bool "Add PCI control unit support of NEC VR4100 series"
depends on MACH_VR41XX && HW_HAS_PCI
default y
select PCI
config MIPS_DB1550
bool "AMD Alchemy DB1550 board"
select SOC_AU1550
select HW_HAS_PCI
select DMA_NONCOHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config VRC4173
tristate "Add NEC VRC4173 companion chip support"
depends on MACH_VR41XX && PCI_VR41XX
---help---
The NEC VRC4173 is a companion chip for NEC VR4122/VR4131.
config MIPS_DB1200
bool "AMD Alchemy DB1200 board"
select SOC_AU1200
select DMA_COHERENT
select MIPS_DISABLE_OBSOLETE_IDE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config TOSHIBA_JMR3927
bool "Support for Toshiba JMR-TX3927 board"
config MIPS_MIRAGE
bool "AMD Alchemy Mirage board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SOC_AU1500
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_COBALT
bool "Support for Cobalt Server"
depends on EXPERIMENTAL
select DMA_NONCOHERENT
select HW_HAS_PCI
select I8259
select IRQ_CPU
select MIPS_GT64111
select SYS_HAS_CPU_NEVADA
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
config MACH_DECSTATION
bool "Support for DECstations"
select BOOT_ELF32
select DMA_NONCOHERENT
select EARLY_PRINTK
select IRQ_CPU
select SYS_HAS_CPU_R3000
select SYS_HAS_CPU_R4X00
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
---help---
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for DEC's MIPS based workstations. For details
see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
DECstation porting pages on <http://decstation.unix-ag.org/>.
......@@ -234,8 +165,10 @@ config MIPS_EV64120
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_GT64120
select SYS_HAS_CPU_R5000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
This is an evaluation board based on the Galileo GT-64120
single-chip system controller that contains a MIPS R5000 compatible
......@@ -243,10 +176,6 @@ config MIPS_EV64120
<http://www.marvell.com/>. Say Y here if you wish to build a
kernel for this platform.
config EVB_PCI1
bool "Enable Second PCI (PCI1)"
depends on MIPS_EV64120
config MIPS_EV96100
bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)"
depends on EXPERIMENTAL
......@@ -256,8 +185,11 @@ config MIPS_EV96100
select MIPS_GT96100
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_R5000
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_BIG_ENDIAN
help
This is an evaluation board based on the Galileo GT-96100 LAN/WAN
communications controllers containing a MIPS R5000 compatible core
......@@ -268,8 +200,11 @@ config MIPS_IVR
bool "Support for Globespan IVR board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select ITE_BOARD_GEN
select SYS_HAS_CPU_NEVADA
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This is an evaluation board built by Globespan to showcase thir
iVR (Internet Video Recorder) design. It utilizes a QED RM5231
......@@ -277,37 +212,16 @@ config MIPS_IVR
located at <http://www.globespan.net/>. Say Y here if you wish to
build a kernel for this platform.
config LASAT
bool "Support for LASAT Networks platforms"
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_GT64120
select R5000_CPU_SCACHE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
config PICVUE
tristate "PICVUE LCD display driver"
depends on LASAT
config PICVUE_PROC
tristate "PICVUE LCD display driver /proc interface"
depends on PICVUE
config DS1603
bool "DS1603 RTC driver"
depends on LASAT
config LASAT_SYSCTL
bool "LASAT sysctl interface"
depends on LASAT
config MIPS_ITE8172
bool "Support for ITE 8172G board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select ITE_BOARD_GEN
select SYS_HAS_CPU_R5432
select SYS_HAS_CPU_NEVADA
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
help
Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
with ATX form factor that utilizes a MIPS R5000 to work with its
......@@ -315,42 +229,86 @@ config MIPS_ITE8172
either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
a kernel for this platform.
config IT8172_REVC
bool "Support for older IT8172 (Rev C)"
depends on MIPS_ITE8172
config MACH_JAZZ
bool "Support for the Jazz family of machines"
select ARC
select ARC32
select ARCH_MAY_HAVE_PC_FDC
select GENERIC_ISA_DMA
select I8259
select ISA
select SYS_HAS_CPU_R4X00
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
help
Say Y here to support the older, Revision C version of the Integrated
Technology Express, Inc. ITE8172 SBC. Vendor page at
<http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
board at <http://www.mvista.com/partners/semiconductor/ite.html>.
This a family of machines based on the MIPS R4030 chipset which was
used by several vendors to build RISC/os and Windows NT workstations.
Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
Olivetti M700-10 workstations.
config LASAT
bool "Support for LASAT Networks platforms"
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_GT64120
select MIPS_NILE4
select R5000_CPU_SCACHE
select SYS_HAS_CPU_R5000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_ATLAS
bool "Support for MIPS Atlas board"
select BOOT_ELF32
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
select MIPS_BOARDS_GEN
select MIPS_BONITO64
select MIPS_GT64120
select MIPS_MSC
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_CPU_NEVADA
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for the QED R5231-based MIPS Atlas evaluation
This enables support for the MIPS Technologies Atlas evaluation
board.
config MIPS_MALTA
bool "Support for MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select HAVE_STD_PC_SERIAL_PORT
select DMA_NONCOHERENT
select IRQ_CPU
select GENERIC_ISA_DMA
select HW_HAS_PCI
select I8259
select MIPS_BOARDS_GEN
select MIPS_BONITO64
select MIPS_GT64120
select MIPS_MSC
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_CPU_NEVADA
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for the VR5000-based MIPS Malta evaluation
This enables support for the MIPS Technologies Malta evaluation
board.
config MIPS_SEAD
......@@ -358,50 +316,64 @@ config MIPS_SEAD
depends on EXPERIMENTAL
select IRQ_CPU
select DMA_NONCOHERENT
select MIPS_BOARDS_GEN
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS64_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for the MIPS Technologies SEAD evaluation
board.
config MOMENCO_OCELOT
bool "Support for Momentum Ocelot board"
config MIPS_SIM
bool 'Support for MIPS simulator (MIPSsim)'
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select MIPS_GT64120
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
help
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
This option enables support for MIPS Technologies MIPSsim software
emulator.
config MOMENCO_OCELOT_G
bool "Support for Momentum Ocelot-G board"
config MOMENCO_JAGUAR_ATX
bool "Support for Momentum Jaguar board"
select BOOT_ELF32
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select IRQ_MV64340
select LIMITED_DMA
select PCI_MARVELL
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM9000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
config MOMENCO_OCELOT_C
bool "Support for Momentum Ocelot-C board"
config MOMENCO_OCELOT
bool "Support for Momentum Ocelot board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_MV64340
select PCI_MARVELL
select IRQ_CPU_RM7K
select MIPS_GT64120
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
......@@ -417,80 +389,95 @@ config MOMENCO_OCELOT_3
select PCI_MARVELL
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM9000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
The Ocelot-3 is based off Discovery III System Controller and
PMC-Sierra Rm79000 core.
config MOMENCO_JAGUAR_ATX
bool "Support for Momentum Jaguar board"
select BOOT_ELF32
config MOMENCO_OCELOT_C
bool "Support for Momentum Ocelot-C board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select IRQ_MV64340
select LIMITED_DMA
select PCI_MARVELL
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
config JAGUAR_DMALOW
bool "Low DMA Mode"
depends on MOMENCO_JAGUAR_ATX
help
Select to Y if jump JP5 is set on your board, N otherwise. Normally
the jumper is set, so if you feel unsafe, just say Y.
config PMC_YOSEMITE
bool "Support for PMC-Sierra Yosemite eval board"
select DMA_COHERENT
config MOMENCO_OCELOT_G
bool "Support for Momentum Ocelot-G board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select IRQ_CPU_RM9K
select PCI_MARVELL
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
Yosemite is an evaluation board for the RM9000x2 processor
manufactured by PMC-Sierra
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
config MIPS_XXS1500
bool "Support for MyCable XXS1500 board"
select DMA_NONCOHERENT
select SOC_AU1500
select SYS_SUPPORTS_LITTLE_ENDIAN
config HYPERTRANSPORT
bool "Hypertransport Support for PMC-Sierra Yosemite"
depends on PMC_YOSEMITE
config PNX8550_V2PCI
bool "Support for Philips PNX8550 based Viper2-PCI board"
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
config PNX8550_JBS
bool "Support for Philips PNX8550 based JBS board"
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
config DDB5074
bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
depends on EXPERIMENTAL
select DDB5XXX_COMMON
select DMA_NONCOHERENT
select HAVE_STD_PC_SERIAL_PORT
select HW_HAS_PCI
select IRQ_CPU
select I8259
select ISA
select SYS_HAS_CPU_R5000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for the VR5000-based NEC DDB Vrc-5074
evaluation board.
config DDB5476
bool "Support for NEC DDB Vrc-5476"
select DDB5XXX_COMMON
select DMA_NONCOHERENT
select HAVE_STD_PC_SERIAL_PORT
select HW_HAS_PCI
select IRQ_CPU
select I8259
select ISA
select SYS_HAS_CPU_R5432
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for the R5432-based NEC DDB Vrc-5476
evaluation board.
......@@ -501,12 +488,15 @@ config DDB5476
config DDB5477
bool "Support for NEC DDB Vrc-5477"
select DDB5XXX_COMMON
select DMA_NONCOHERENT
select HW_HAS_PCI
select I8259
select IRQ_CPU
select SYS_HAS_CPU_R5432
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for the R5432-based NEC DDB Vrc-5477,
or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
......@@ -514,10 +504,28 @@ config DDB5477
Features : kernel debugging, serial terminal, NFS root fs, on-board
ether port USB, AC97, PCI, etc.
config DDB5477_BUS_FREQUENCY
int "bus frequency (in kHZ, 0 for auto-detect)"
depends on DDB5477
default 0
config MACH_VR41XX
bool "Support for NEC VR4100 series based machines"
select SYS_HAS_CPU_VR41XX
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
config PMC_YOSEMITE
bool "Support for PMC-Sierra Yosemite eval board"
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select IRQ_CPU_RM9K
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM9000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
help
Yosemite is an evaluation board for the RM9000x2 processor
manufactured by PMC-Sierra.
config QEMU
bool "Support for Qemu"
......@@ -527,15 +535,16 @@ config QEMU
select I8259
select ISA
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
Qemu is a software emulator which among other architectures also
can simulate a MIPS32 4Kc system. This patch adds support for the
system architecture that currently is being simulated by Qemu. It
will eventually be removed again when Qemu has the capability to
simulate actual MIPS hardware platforms. More information on Qemu
can be found at http://www.linux-mips.org/wiki/Qemu.
Qemu is a software emulator which among other architectures also
can simulate a MIPS32 4Kc system. This patch adds support for the
system architecture that currently is being simulated by Qemu. It
will eventually be removed again when Qemu has the capability to
simulate actual MIPS hardware platforms. More information on Qemu
can be found at http://www.linux-mips.org/wiki/Qemu.
config SGI_IP22
bool "Support for SGI IP22 (Indy/Indigo2)"
......@@ -543,11 +552,15 @@ config SGI_IP22
select ARC32
select BOOT_ELF32
select DMA_NONCOHERENT
select HW_HAS_EISA
select IP22_CPU_SCACHE
select IRQ_CPU
select SWAP_IO_SPACE
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
This are the SGI Indy, Challenge S and Indigo2, as well as certain
OEM variants like the Tandem CMN B006S. To compile a Linux kernel
......@@ -557,70 +570,18 @@ config SGI_IP27
bool "Support for SGI IP27 (Origin200/2000)"
select ARC
select ARC64
select BOOT_ELF64
select DMA_IP27
select HW_HAS_PCI
select PCI_DOMAINS
select SYS_HAS_CPU_R10000
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
workstations. To compile a Linux kernel that runs on these, say Y
here.
#config SGI_SN0_XXL
# bool "IP27 XXL"
# depends on SGI_IP27
# This options adds support for userspace processes upto 16TB size.
# Normally the limit is just .5TB.
config SGI_SN0_N_MODE
bool "IP27 N-Mode"
depends on SGI_IP27
help
The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
configured in either N-Modes which allows for more nodes or M-Mode
which allows for more memory. Your system is most probably
running in M-Mode, so you should say N here.
config ARCH_DISCONTIGMEM_ENABLE
bool
default y if SGI_IP27
help
Say Y to upport efficient handling of discontiguous physical memory,
for architectures which are either NUMA (Non-Uniform Memory Access)
or have huge holes in the physical address space for other reasons.
See <file:Documentation/vm/numa> for more.
config NUMA
bool "NUMA Support"
depends on SGI_IP27
help
Say Y to compile the kernel to support NUMA (Non-Uniform Memory
Access). This option is for configuring high-end multiprocessor
server machines. If in doubt, say N.
config MAPPED_KERNEL
bool "Mapped kernel support"
depends on SGI_IP27
help
Change the way a Linux kernel is loaded into memory on a MIPS64
machine. This is required in order to support text replication and
NUMA. If you need to understand it, read the source code.
config REPLICATE_KTEXT
bool "Kernel text replication support"
depends on SGI_IP27
help
Say Y here to enable replicating the kernel text across multiple
nodes in a NUMA cluster. This trades memory for speed.
config REPLICATE_EXHANDLERS
bool "Exception handler replication support"
depends on SGI_IP27
help
Say Y here to enable replicating the kernel exception handlers
across multiple nodes in a NUMA cluster. This trades memory for
speed.
config SGI_IP32
bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
depends on EXPERIMENTAL
......@@ -633,353 +594,152 @@ config SGI_IP32
select HW_HAS_PCI
select R5000_CPU_SCACHE
select RM7000_CPU_SCACHE
select SYS_HAS_CPU_R5000
select SYS_HAS_CPU_R10000 if BROKEN
select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
If you want this kernel to run on SGI O2 workstation, say Y here.
config SOC_AU1X00
bool "Support for AMD/Alchemy Au1X00 SOCs"
select SYS_SUPPORTS_32BIT_KERNEL
choice
prompt "Au1X00 SOC Type"
depends on SOC_AU1X00
help
Say Y here to enable support for one of three AMD/Alchemy
SOCs. For additional documentation see www.amd.com.
config SOC_AU1000
bool "SOC_AU1000"
config SOC_AU1100
bool "SOC_AU1100"
config SOC_AU1500
bool "SOC_AU1500"
config SOC_AU1550
bool "SOC_AU1550"
endchoice
choice
prompt "AMD/Alchemy Au1x00 board support"
depends on SOC_AU1X00
help
These are evaluation boards built by AMD/Alchemy to
showcase their Au1X00 Internet Edge Processors. The SOC design
is based on the MIPS32 architecture running at 266/400/500MHz
with many integrated peripherals. Further information can be
found at their website, <http://www.amd.com/>. Say Y here if you
wish to build a kernel for this platform.
config MIPS_PB1000
bool "PB1000 board"
depends on SOC_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
config MIPS_PB1100
bool "PB1100 board"
depends on SOC_AU1100
select DMA_NONCOHERENT
select HW_HAS_PCI
select SWAP_IO_SPACE
config MIPS_PB1500
bool "PB1500 board"
depends on SOC_AU1500
select DMA_COHERENT
select HW_HAS_PCI
config MIPS_PB1550
bool "PB1550 board"
depends on SOC_AU1550
select DMA_COHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
config MIPS_DB1000
bool "DB1000 board"
depends on SOC_AU1000
select DMA_NONCOHERENT
select HW_HAS_PCI
config MIPS_DB1100
bool "DB1100 board"
depends on SOC_AU1100
select DMA_NONCOHERENT
config MIPS_DB1500
bool "DB1500 board"
depends on SOC_AU1500
select DMA_COHERENT
select HW_HAS_PCI
select MIPS_DISABLE_OBSOLETE_IDE
config MIPS_DB1550
bool "DB1550 board"
depends on SOC_AU1550
select HW_HAS_PCI
select DMA_COHERENT
select MIPS_DISABLE_OBSOLETE_IDE
config MIPS_BOSPORUS
bool "Bosporus board"
depends on SOC_AU1500
select DMA_NONCOHERENT
config MIPS_MIRAGE
bool "Mirage board"
depends on SOC_AU1500
select DMA_NONCOHERENT
config MIPS_XXS1500
bool "MyCable XXS1500 board"
depends on SOC_AU1500
select DMA_NONCOHERENT
config MIPS_MTX1
bool "4G Systems MTX-1 board"
depends on SOC_AU1500
select HW_HAS_PCI
select DMA_NONCOHERENT
endchoice
config SIBYTE_SB1xxx_SOC
bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)"
depends on EXPERIMENTAL
config SIBYTE_BIGSUR
bool "Support for Sibyte BigSur"
select BOOT_ELF32
select DMA_COHERENT
select PCI_DOMAINS
select SIBYTE_BCM1x80
select SWAP_IO_SPACE
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
choice
prompt "BCM1xxx SOC-based board"
depends on SIBYTE_SB1xxx_SOC
default SIBYTE_SWARM
help
Enable support for boards based on the SiByte line of SOCs
from Broadcom. There are configurations for the known
evaluation boards, or you can choose "Other" and add your
own board support code.
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_SWARM
bool "BCM91250A-SWARM"
bool "Support for Sibyte BCM91250A-SWARM"
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_SENTOSA
bool "BCM91250E-Sentosa"
bool "Support for Sibyte BCM91250E-Sentosa"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_RHONE
bool "BCM91125E-Rhone"
bool "Support for Sibyte BCM91125E-Rhone"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1125H
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_CARMEL
bool "BCM91120x-Carmel"
bool "Support for Sibyte BCM91120x-Carmel"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_PTSWARM
bool "BCM91250PT-PTSWARM"
bool "Support for Sibyte BCM91250PT-PTSWARM"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_LITTLESUR
bool "BCM91250C2-LittleSur"
bool "Support for Sibyte BCM91250C2-LittleSur"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_CRHINE
bool "BCM91120C-CRhine"
bool "Support for Sibyte BCM91120C-CRhine"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_CRHONE
bool "BCM91125C-CRhone"
select SIBYTE_BCM1125
config SIBYTE_UNKNOWN
bool "Other"
endchoice
config SIBYTE_BOARD
bool
depends on SIBYTE_SB1xxx_SOC && !SIBYTE_UNKNOWN
default y
choice
prompt "BCM1xxx SOC Type"
depends on SIBYTE_UNKNOWN
default SIBYTE_UNK_BCM1250
help
Since you haven't chosen a known evaluation board from
Broadcom, you must explicitly pick the SOC this kernel is
targetted for.
config SIBYTE_UNK_BCM1250
bool "BCM1250"
select SIBYTE_SB1250
config SIBYTE_UNK_BCM1120
bool "BCM1120"
select SIBYTE_BCM1120
config SIBYTE_UNK_BCM1125
bool "BCM1125"
bool "Support for Sibyte BCM91125C-CRhone"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
select SIBYTE_BCM1125
config SIBYTE_UNK_BCM1125H
bool "BCM1125H"
select SIBYTE_BCM1125H
endchoice
config SIBYTE_SB1250
bool
select HW_HAS_PCI
config SIBYTE_BCM1120
bool
select SIBYTE_BCM112X
config SIBYTE_BCM1125
bool
select HW_HAS_PCI
select SIBYTE_BCM112X
config SIBYTE_BCM1125H
bool
select HW_HAS_PCI
select SIBYTE_BCM112X
config SIBYTE_BCM112X
bool
choice
prompt "SiByte SOC Stepping"
depends on SIBYTE_SB1xxx_SOC
config CPU_SB1_PASS_1
bool "1250 Pass1"
depends on SIBYTE_SB1250
select CPU_HAS_PREFETCH
config CPU_SB1_PASS_2_1250
bool "1250 An"
depends on SIBYTE_SB1250
select CPU_SB1_PASS_2
help
Also called BCM1250 Pass 2
config CPU_SB1_PASS_2_2
bool "1250 Bn"
depends on SIBYTE_SB1250
select CPU_HAS_PREFETCH
help
Also called BCM1250 Pass 2.2
config CPU_SB1_PASS_4
bool "1250 Cn"
depends on SIBYTE_SB1250
select CPU_HAS_PREFETCH
help
Also called BCM1250 Pass 3
config CPU_SB1_PASS_2_112x
bool "112x Hybrid"
depends on SIBYTE_BCM112X
select CPU_SB1_PASS_2
config CPU_SB1_PASS_3
bool "112x An"
depends on SIBYTE_BCM112X
select CPU_HAS_PREFETCH
endchoice
config CPU_SB1_PASS_2
bool
config SIBYTE_HAS_LDT
bool
depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
default y
config SIMULATION
bool "Running under simulation"
depends on SIBYTE_SB1xxx_SOC
help
Build a kernel suitable for running under the GDB simulator.
Primarily adjusts the kernel's notion of time.
config SIBYTE_CFE
bool "Booting from CFE"
depends on SIBYTE_SB1xxx_SOC
help
Make use of the CFE API for enumerating available memory,
controlling secondary CPUs, and possibly console output.
config SIBYTE_CFE_CONSOLE
bool "Use firmware console"
depends on SIBYTE_CFE
help
Use the CFE API's console write routines during boot. Other console
options (VT console, sb1250 duart console, etc.) should not be
configured.
config SIBYTE_STANDALONE
bool
depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
default y
config SIBYTE_STANDALONE_RAM_SIZE
int "Memory size (in megabytes)"
depends on SIBYTE_STANDALONE
default "32"
config SIBYTE_BUS_WATCHER
bool "Support for Bus Watcher statistics"
depends on SIBYTE_SB1xxx_SOC
help
Handle and keep statistics on the bus error interrupts (COR_ECC,
BAD_ECC, IO_BUS).
config SIBYTE_BW_TRACE
bool "Capture bus trace before bus error"
depends on SIBYTE_BUS_WATCHER
help
Run a continuous bus trace, dumping the raw data as soon as
a ZBbus error is detected. Cannot work if ZBbus profiling
is turned on, and also will interfere with JTAG-based trace
buffer activity. Raw buffer data is dumped to console, and
must be processed off-line.
config SIBYTE_SB1250_PROF
bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
depends on SIBYTE_SB1xxx_SOC
config SIBYTE_TBPROF
bool "Support for ZBbus profiling"
depends on SIBYTE_SB1xxx_SOC
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
config SNI_RM200_PCI
bool "Support for SNI RM200 PCI"
select ARC
select ARC32
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select HAVE_STD_PC_SERIAL_PORT
select HW_HAS_EISA
select HW_HAS_PCI
select I8259
select ISA
select SYS_HAS_CPU_R4X00
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
help
The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
Nixdorf Informationssysteme (SNI), parent company of Pyramid
Technology and now in turn merged with Fujitsu. Say Y here to
support this machine type.
config TOSHIBA_JMR3927
bool "Support for Toshiba JMR-TX3927 board"
select DMA_NONCOHERENT
select HW_HAS_PCI
select MIPS_TX3927
select SWAP_IO_SPACE
select SYS_HAS_CPU_TX39XX
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select TOSHIBA_BOARDS
config TOSHIBA_RBTX4927
bool "Support for Toshiba TBTX49[23]7 board"
select DMA_NONCOHERENT
......@@ -988,15 +748,51 @@ config TOSHIBA_RBTX4927
select I8259
select ISA
select SWAP_IO_SPACE
select SYS_HAS_CPU_TX49XX
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select TOSHIBA_BOARDS
help
This Toshiba board is based on the TX4927 processor. Say Y here to
support this machine type
config TOSHIBA_FPCIB0
bool "FPCIB0 Backplane Support"
depends on TOSHIBA_RBTX4927
config TOSHIBA_RBTX4938
bool "Support for Toshiba RBTX4938 board"
select HAVE_STD_PC_SERIAL_PORT
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select HAS_TXX9_SERIAL
select HW_HAS_PCI
select I8259
select ISA
select SWAP_IO_SPACE
select SYS_HAS_CPU_TX49XX
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
select TOSHIBA_BOARDS
help
This Toshiba board is based on the TX4938 processor. Say Y here to
support this machine type
endchoice
source "arch/mips/ddb5xxx/Kconfig"
source "arch/mips/gt64120/ev64120/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/ite-boards/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/momentum/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
source "arch/mips/tx4927/Kconfig"
source "arch/mips/tx4938/Kconfig"
source "arch/mips/vr41xx/Kconfig"
source "arch/mips/philips/pnx8550/common/Kconfig"
endmenu
config RWSEM_GENERIC_SPINLOCK
bool
......@@ -1014,8 +810,9 @@ config GENERIC_CALIBRATE_DELAY
#
config ARC
bool
depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61
default y
config ARCH_MAY_HAVE_PC_FDC
bool
config DMA_COHERENT
bool
......@@ -1034,51 +831,65 @@ config DMA_NONCOHERENT
config DMA_NEED_PCI_MAP_STATE
bool
config OWN_DMA
bool
config EARLY_PRINTK
bool
depends on MACH_DECSTATION
default y
config GENERIC_ISA_DMA
bool
depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 || MIPS_MALTA
default y
config I8259
bool
depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MACH_JAZZ || MIPS_MALTA || MIPS_COBALT
default y
config LIMITED_DMA
bool
select HIGHMEM
select SYS_SUPPORTS_HIGHMEM
config MIPS_BONITO64
bool
depends on MIPS_ATLAS || MIPS_MALTA
default y
config MIPS_MSC
bool
depends on MIPS_ATLAS || MIPS_MALTA
default y
config MIPS_NILE4
bool
depends on LASAT
default y
config MIPS_DISABLE_OBSOLETE_IDE
bool
config CPU_LITTLE_ENDIAN
bool "Generate little endian code"
default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA
default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927
#
# Endianess selection. Suffiently obscure so many users don't know what to
# answer,so we try hard to limit the available choices. Also the use of a
# choice statement should be more obvious to the user.
#
choice
prompt "Endianess selection"
help
Some MIPS machines can be configured for either little or big endian
byte order. These modes require different kernels. Say Y if your
machine is little endian, N if it's a big endian machine.
byte order. These modes require different kernels and a different
Linux distribution. In general there is one prefered byteorder for a
particular system but some systems are just as commonly used in the
one or the other endianess.
config CPU_BIG_ENDIAN
bool "Big endian"
depends on SYS_SUPPORTS_BIG_ENDIAN
config CPU_LITTLE_ENDIAN
bool "Little endian"
depends on SYS_SUPPORTS_LITTLE_ENDIAN
help
endchoice
config SYS_SUPPORTS_BIG_ENDIAN
bool
config SYS_SUPPORTS_LITTLE_ENDIAN
bool
config IRQ_CPU
bool
......@@ -1086,42 +897,69 @@ config IRQ_CPU
config IRQ_CPU_RM7K
bool
config IRQ_CPU_RM9K
bool
config IRQ_MV64340
bool
config DDB5XXX_COMMON
bool
depends on DDB5074 || DDB5476 || DDB5477
default y
config MIPS_BOARDS_GEN
bool
depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD
default y
config MIPS_GT64111
bool
depends on MIPS_COBALT
default y
config MIPS_GT64120
bool
depends on MIPS_EV64120 || MIPS_EV96100 || LASAT || MIPS_ATLAS || MIPS_MALTA || MOMENCO_OCELOT
default y
config MIPS_TX3927
bool
depends on TOSHIBA_JMR3927
select HAS_TXX9_SERIAL
default y
config PCI_MARVELL
bool
config ITE_BOARD_GEN
bool
depends on MIPS_IVR || MIPS_ITE8172
default y
config SOC_AU1000
bool
select SOC_AU1X00
config SOC_AU1100
bool
select SOC_AU1X00
config SOC_AU1500
bool
select SOC_AU1X00
config SOC_AU1550
bool
select SOC_AU1X00
config SOC_AU1200
bool
select SOC_AU1X00
config SOC_AU1X00
bool
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
config PNX8550
bool
select SOC_PNX8550
config SOC_PNX8550
bool
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_CPU_R4X00
select SYS_SUPPORTS_32BIT_KERNEL
config SWAP_IO_SPACE
bool
......@@ -1148,6 +986,9 @@ config SYSCLK_100
endchoice
config ARC32
bool
config AU1X00_USB_DEVICE
bool
depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
......@@ -1155,11 +996,7 @@ config AU1X00_USB_DEVICE
config MIPS_GT96100
bool
depends on MIPS_EV96100
default y
help
Say Y here to support the Galileo Technology GT96100 communications
controller card. There is a web page at <http://www.galileot.com/>.
select MIPS_GT64120
config IT8172_CIR
bool
......@@ -1173,8 +1010,6 @@ config IT8712
config BOOT_ELF32
bool
depends on MACH_DECSTATION || MIPS_ATLAS || MIPS_MALTA || MOMENCO_JAGUAR_ATX || MOMENCO_OCELOT_3 || SIBYTE_SB1xxx_SOC || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI
default y
config MIPS_L1_CACHE_SHIFT
int
......@@ -1182,11 +1017,6 @@ config MIPS_L1_CACHE_SHIFT
default "7" if SGI_IP27
default "5"
config ARC32
bool
depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
default y
config HAVE_STD_PC_SERIAL_PORT
bool
......@@ -1206,30 +1036,12 @@ config ARC_PROMLIB
config ARC64
bool
depends on SGI_IP27
default y
config BOOT_ELF64
bool
depends on SGI_IP27
default y
#config MAPPED_PCI_IO y
# bool
# depends on SGI_IP27
# default y
config QL_ISP_A64
bool
depends on SGI_IP27
default y
config TOSHIBA_BOARDS
bool
depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
default y
endmenu
menu "CPU selection"
......@@ -1237,18 +1049,69 @@ choice
prompt "CPU type"
default CPU_R4X00
config CPU_MIPS32
bool "MIPS32"
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
help
Choose this option to build a kernel for release 1 or later of the
MIPS32 architecture. Most modern embedded systems with a 32-bit
MIPS processor are based on a MIPS32 processor. If you know the
specific type of processor in your system, choose those that one
otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
Release 2 of the MIPS32 architecture is available since several
years so chances are you even have a MIPS32 Release 2 processor
in which case you should choose CPU_MIPS32_R2 instead for better
performance.
config CPU_MIPS32_R2
bool "MIPS32 Release 2"
depends on SYS_HAS_CPU_MIPS32_R2
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
help
Choose this option to build a kernel for release 2 or later of the
MIPS32 architecture. Most modern embedded systems with a 32-bit
MIPS processor are based on a MIPS32 processor. If you know the
specific type of processor in your system, choose those that one
otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
config CPU_MIPS64
bool "MIPS64"
config CPU_MIPS64_R1
bool "MIPS64 Release 1"
depends on SYS_HAS_CPU_MIPS64_R1
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
Choose this option to build a kernel for release 1 or later of the
MIPS64 architecture. Many modern embedded systems with a 64-bit
MIPS processor are based on a MIPS64 processor. If you know the
specific type of processor in your system, choose those that one
otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
Release 2 of the MIPS64 architecture is available since several
years so chances are you even have a MIPS64 Release 2 processor
in which case you should choose CPU_MIPS64_R2 instead for better
performance.
config CPU_MIPS64_R2
bool "MIPS64 Release 2"
depends on SYS_HAS_CPU_MIPS64_R2
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
Choose this option to build a kernel for release 2 or later of the
MIPS64 architecture. Many modern embedded systems with a 64-bit
MIPS processor are based on a MIPS64 processor. If you know the
specific type of processor in your system, choose those that one
otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
config CPU_R3000
bool "R3000"
depends on SYS_HAS_CPU_R3000
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
help
Please make sure to pick the right CPU type. Linux/MIPS is not
designed to be generic, i.e. Kernels compiled for R3000 CPUs will
......@@ -1259,20 +1122,23 @@ config CPU_R3000
config CPU_TX39XX
bool "R39XX"
depends on SYS_HAS_CPU_TX39XX
select CPU_SUPPORTS_32BIT_KERNEL
config CPU_VR41XX
bool "R41xx"
depends on SYS_HAS_CPU_VR41XX
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
The options selects support for the NEC VR41xx series of processors.
The options selects support for the NEC VR4100 series of processors.
Only choose this option if you have one of these processors as a
kernel built with this option will not run on any other type of
processor or vice versa.
config CPU_R4300
bool "R4300"
depends on SYS_HAS_CPU_R4300
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1280,6 +1146,7 @@ config CPU_R4300
config CPU_R4X00
bool "R4x00"
depends on SYS_HAS_CPU_R4X00
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1288,11 +1155,13 @@ config CPU_R4X00
config CPU_TX49XX
bool "R49XX"
depends on SYS_HAS_CPU_TX49XX
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
config CPU_R5000
bool "R5000"
depends on SYS_HAS_CPU_R5000
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1300,10 +1169,14 @@ config CPU_R5000
config CPU_R5432
bool "R5432"
depends on SYS_HAS_CPU_R5432
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
config CPU_R6000
bool "R6000"
depends on EXPERIMENTAL
depends on SYS_HAS_CPU_R6000
select CPU_SUPPORTS_32BIT_KERNEL
help
MIPS Technologies R6000 and R6000A series processors. Note these
......@@ -1311,6 +1184,7 @@ config CPU_R6000
config CPU_NEVADA
bool "RM52xx"
depends on SYS_HAS_CPU_NEVADA
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1319,6 +1193,8 @@ config CPU_NEVADA
config CPU_R8000
bool "R8000"
depends on EXPERIMENTAL
depends on SYS_HAS_CPU_R8000
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_64BIT_KERNEL
help
MIPS Technologies R8000 processors. Note these processors are
......@@ -1326,25 +1202,151 @@ config CPU_R8000
config CPU_R10000
bool "R10000"
depends on SYS_HAS_CPU_R10000
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
help
MIPS Technologies R10000-series processors.
config CPU_RM7000
bool "RM7000"
depends on SYS_HAS_CPU_RM7000
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
config CPU_RM9000
bool "RM9000"
depends on SYS_HAS_CPU_RM9000
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
config CPU_SB1
bool "SB1"
depends on SYS_HAS_CPU_SB1
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
endchoice
config SYS_HAS_CPU_MIPS32_R1
bool
config SYS_HAS_CPU_MIPS32_R2
bool
config SYS_HAS_CPU_MIPS64_R1
bool
config SYS_HAS_CPU_MIPS64_R2
bool
config SYS_HAS_CPU_R3000
bool
config SYS_HAS_CPU_TX39XX
bool
config SYS_HAS_CPU_VR41XX
bool
config SYS_HAS_CPU_R4300
bool
config SYS_HAS_CPU_R4X00
bool
config SYS_HAS_CPU_TX49XX
bool
config SYS_HAS_CPU_R5000
bool
config SYS_HAS_CPU_R5432
bool
config SYS_HAS_CPU_R6000
bool
config SYS_HAS_CPU_NEVADA
bool
config SYS_HAS_CPU_R8000
bool
config SYS_HAS_CPU_R10000
bool
config SYS_HAS_CPU_RM7000
bool
config SYS_HAS_CPU_RM9000
bool
config SYS_HAS_CPU_SB1
bool
endmenu
#
# These two indicate any levelof the MIPS32 and MIPS64 architecture
#
config CPU_MIPS32
bool
default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
config CPU_MIPS64
bool
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
#
# These two indicate the revision of the architecture, either 32 bot 64 bit.
#
config CPU_MIPSR1
bool
default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
config CPU_MIPSR2
bool
default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
config SYS_SUPPORTS_32BIT_KERNEL
bool
config SYS_SUPPORTS_64BIT_KERNEL
bool
config CPU_SUPPORTS_32BIT_KERNEL
bool
config CPU_SUPPORTS_64BIT_KERNEL
bool
menu "Kernel type"
choice
prompt "Kernel code model"
help
You should only select this option if you have a workload that
actually benefits from 64-bit processing or if your machine has
large memory. You will only be presented a single option in this
menu if your system does not support both 32-bit and 64-bit kernels.
config 32BIT
bool "32-bit kernel"
depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
select TRAD_SIGNALS
help
Select this option if you want to build a 32-bit kernel.
config 64BIT
bool "64-bit kernel"
depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
help
Select this option if you want to build a 64-bit kernel.
endchoice
......@@ -1416,12 +1418,43 @@ config SIBYTE_DMA_PAGEOPS
SiByte Linux port. Seems to give a small performance benefit.
config CPU_HAS_PREFETCH
bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2
default y if CPU_MIPS32 || CPU_MIPS64 || CPU_RM7000 || CPU_RM9000 || CPU_R10000
bool
config MIPS_MT
bool "Enable MIPS MT"
config VTAG_ICACHE
bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32
default y if CPU_SB1
choice
prompt "MIPS MT options"
depends on MIPS_MT
config MIPS_MT_SMP
bool "Use 1 TC on each available VPE for SMP"
select SMP
config MIPS_VPE_LOADER
bool "VPE loader support."
depends on MIPS_MT
help
Includes a loader for loading an elf relocatable object
onto another VPE and running it.
endchoice
config MIPS_VPE_LOADER_TOM
bool "Load VPE program into memory hidden from linux"
depends on MIPS_VPE_LOADER
default y
help
The loader can use memory that is present but has been hidden from
Linux using the kernel command line option "mem=xxMB". It's up to
you to ensure the amount you put in the option and the space your
program requires is less or equal to the amount physically present.
# this should possibly be in drivers/char, but it is rather cpu related. Hmmm
config MIPS_VPE_APSP_API
bool "Enable support for AP/SP API (RTLX)"
depends on MIPS_VPE_LOADER
help
config SB1_PASS_1_WORKAROUNDS
bool
......@@ -1440,7 +1473,7 @@ config SB1_PASS_2_1_WORKAROUNDS
config 64BIT_PHYS_ADDR
bool "Support for 64-bit physical address space"
depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT
depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32_R1 || CPU_MIPS64_R1) && 32BIT
config CPU_ADVANCED
bool "Override CPU Options"
......@@ -1463,7 +1496,7 @@ config CPU_HAS_LLSC
config CPU_HAS_LLDSCD
bool "lld/scd Instructions available" if CPU_ADVANCED
default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32
default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32_R1
help
Say Y here if your CPU has the lld and scd instructions, the 64-bit
equivalents of ll and sc. Say Y here for better performance, N if
......@@ -1477,11 +1510,51 @@ config CPU_HAS_WB
machines which require flushing of write buffers in software. Saying
Y is the safe option; N may result in kernel malfunction and crashes.
menu "MIPSR2 Interrupt handling"
depends on CPU_MIPSR2 && CPU_ADVANCED
config CPU_MIPSR2_IRQ_VI
bool "Vectored interrupt mode"
help
Vectored interrupt mode allowing faster dispatching of interrupts.
The board support code needs to be written to take advantage of this
mode. Compatibility code is included to allow the kernel to run on
a CPU that does not support vectored interrupts. It's safe to
say Y here.
config CPU_MIPSR2_IRQ_EI
bool "External interrupt controller mode"
help
Extended interrupt mode takes advantage of an external interrupt
controller to allow fast dispatching from many possible interrupt
sources. Say N unless you know that external interrupt support is
required.
config CPU_MIPSR2_SRS
bool "Make shadow set registers available for interrupt handlers"
depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI
help
Allow the kernel to use shadow register sets for fast interrupts.
Interrupt handlers must be specially written to use shadow sets.
Say N unless you know that shadow register set upport is needed.
endmenu
config CPU_HAS_SYNC
bool
depends on !CPU_R3000
default y
#
# Use the generic interrupt handling code in kernel/irq/:
#
config GENERIC_HARDIRQS
bool
default y
config GENERIC_IRQ_PROBE
bool
default y
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
......@@ -1491,14 +1564,19 @@ config CPU_HAS_SYNC
# where it's known to be safe. This will not offer highmem on a few systems
# such as MIPS32 and MIPS64 CPUs which may have virtual and physically
# indexed CPUs but we're playing safe.
# - We should not offer highmem for system of which we already know that they
# don't have memory configurations that could gain from highmem support in
# the kernel because they don't support configurations with RAM at physical
# addresses > 0x20000000.
# - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
# know they might have memory configurations that could make use of highmem
# support.
#
config HIGHMEM
bool "High Memory Support"
depends on 32BIT && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX)
depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
config CPU_SUPPORTS_HIGHMEM
bool
config SYS_SUPPORTS_HIGHMEM
bool
config ARCH_FLATMEM_ENABLE
def_bool y
......@@ -1508,7 +1586,7 @@ source "mm/Kconfig"
config SMP
bool "Multi-Processing support"
depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27
depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP
---help---
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
......@@ -1543,14 +1621,7 @@ config NR_CPUS
This is purely to save memory - each supported CPU adds
approximately eight kilobytes to the kernel image.
config PREEMPT
bool "Preemptible Kernel"
help
This option reduces the latency of the kernel when reacting to
real-time or interactive events by allowing a low priority process to
be preempted even if it is in kernel mode executing a system call.
This allows applications to run more reliably even when the system is
under load.
source "kernel/Kconfig.preempt"
config RTC_DS1742
bool "DS1742 BRAM/RTC support"
......@@ -1566,14 +1637,16 @@ config MIPS_INSANE_LARGE
This will result in additional memory usage, so it is not
recommended for normal users.
endmenu
config RWSEM_GENERIC_SPINLOCK
bool
default y
endmenu
menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
config HW_HAS_EISA
bool
config HW_HAS_PCI
bool
......@@ -1607,7 +1680,7 @@ config ISA
config EISA
bool "EISA support"
depends on SGI_IP22 || SNI_RM200_PCI
depends on HW_HAS_EISA
select ISA
---help---
The Extended Industry Standard Architecture (EISA) bus was
......@@ -1641,12 +1714,6 @@ config MMU
bool
default y
config MCA
bool
config SBUS
bool
source "drivers/pcmcia/Kconfig"
source "drivers/pci/hotplug/Kconfig"
......@@ -1659,7 +1726,6 @@ source "fs/Kconfig.binfmt"
config TRAD_SIGNALS
bool
default y if 32BIT
config BUILD_ELF64
bool "Use 64-bit ELF format for building"
......@@ -1678,7 +1744,7 @@ config BUILD_ELF64
config BINFMT_IRIX
bool "Include IRIX binary compatibility"
depends on !CPU_LITTLE_ENDIAN && 32BIT && BROKEN
depends on CPU_BIG_ENDIAN && 32BIT && BROKEN
config MIPS32_COMPAT
bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
......@@ -1718,9 +1784,26 @@ config BINFMT_ELF32
bool
default y if MIPS32_O32 || MIPS32_N32
config SECCOMP
bool "Enable seccomp to safely compute untrusted bytecode"
depends on PROC_FS && BROKEN
default y
help
This kernel feature is useful for number crunching applications
that may need to compute untrusted bytecode during their
execution. By using pipes or other transports made available to
the process as file descriptors supporting the read/write
syscalls, it's possible to isolate those applications in
their own address space using seccomp. Once seccomp is
enabled via /proc/<pid>/seccomp, it cannot be disabled
and the task is only allowed to execute a few safe syscalls
defined by each seccomp mode.
If unsure, say Y. Only embedded should say N here.
config PM
bool "Power Management support (EXPERIMENTAL)"
depends on EXPERIMENTAL && MACH_AU1X00
depends on EXPERIMENTAL && SOC_AU1X00
endmenu
......@@ -1730,6 +1813,8 @@ source "drivers/Kconfig"
source "fs/Kconfig"
source "arch/mips/oprofile/Kconfig"
source "arch/mips/Kconfig.debug"
source "security/Kconfig"
......@@ -1737,18 +1822,3 @@ source "security/Kconfig"
source "crypto/Kconfig"
source "lib/Kconfig"
#
# Use the generic interrupt handling code in kernel/irq/:
#
config GENERIC_HARDIRQS
bool
default y
config GENERIC_IRQ_PROBE
bool
default y
config ISA_DMA_API
bool
default y
......@@ -52,6 +52,21 @@ ifdef CONFIG_CROSSCOMPILE
CROSS_COMPILE := $(tool-prefix)
endif
CHECKFLAGS-y += -D__linux__ -D__mips__ \
-D_ABIO32=1 \
-D_ABIN32=2 \
-D_ABI64=3
CHECKFLAGS-$(CONFIG_32BIT) += -D_MIPS_SIM=_ABIO32 \
-D_MIPS_SZLONG=32 \
-D__PTRDIFF_TYPE__=int
CHECKFLAGS-$(CONFIG_64BIT) += -m64 -D_MIPS_SIM=_ABI64 \
-D_MIPS_SZLONG=64 \
-D__PTRDIFF_TYPE__="long int"
CHECKFLAGS-$(CONFIG_CPU_BIG_ENDIAN) += -D__MIPSEB__
CHECKFLAGS-$(CONFIG_CPU_LITTLE_ENDIAN) += -D__MIPSEL__
CHECKFLAGS = $(CHECKFLAGS-y)
ifdef CONFIG_BUILD_ELF64
gas-abi = 64
ld-emul = $(64bit-emul)
......@@ -79,9 +94,18 @@ endif
cflags-y += -I $(TOPDIR)/include/asm/gcc
cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
cflags-y += $(call cc-option, -finline-limit=100000)
LDFLAGS_vmlinux += -G 0 -static -n
LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
MODFLAGS += -mlong-calls
#
# We explicitly add the endianness specifier if needed, this allows
# to compile kernels with a toolchain for the other endianness. We
# carefully avoid to add it redundantly because gcc 3.3/3.4 complains
# when fed the toolchain default!
#
cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB)
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL)
cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
#
......@@ -167,14 +191,22 @@ cflags-$(CONFIG_CPU_TX49XX) += \
$(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \
-Wa,--trap
cflags-$(CONFIG_CPU_MIPS32) += \
cflags-$(CONFIG_CPU_MIPS32_R1) += \
$(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
-Wa,--trap
cflags-$(CONFIG_CPU_MIPS64) += \
cflags-$(CONFIG_CPU_MIPS32_R2) += \
$(call set_gccflags,mips32r2,mips32r2,r4600,mips3,mips2) \
-Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R1) += \
$(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \
-Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R2) += \
$(call set_gccflags,mips64r2,mips64r2,r4600,mips3,mips2) \
-Wa,--trap
cflags-$(CONFIG_CPU_R5000) += \
$(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \
-Wa,--trap
......@@ -196,6 +228,7 @@ cflags-$(CONFIG_CPU_RM9000) += \
$(call set_gccflags,rm9000,mips4,r5000,mips4,mips2) \
-Wa,--trap
cflags-$(CONFIG_CPU_SB1) += \
$(call set_gccflags,sb1,mips64,r5000,mips4,mips2) \
-Wa,--trap
......@@ -265,6 +298,13 @@ libs-$(CONFIG_MIPS_PB1550) += arch/mips/au1000/pb1550/
cflags-$(CONFIG_MIPS_PB1550) += -Iinclude/asm-mips/mach-pb1x00
load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
#
# AMD Alchemy Pb1200 eval board
#
libs-$(CONFIG_MIPS_PB1200) += arch/mips/au1000/pb1200/
cflags-$(CONFIG_MIPS_PB1200) += -Iinclude/asm-mips/mach-pb1x00
load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
#
# AMD Alchemy Db1000 eval board
#
......@@ -293,6 +333,13 @@ libs-$(CONFIG_MIPS_DB1550) += arch/mips/au1000/db1x00/
cflags-$(CONFIG_MIPS_DB1550) += -Iinclude/asm-mips/mach-db1x00
load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
#
# AMD Alchemy Db1200 eval board
#
libs-$(CONFIG_MIPS_DB1200) += arch/mips/au1000/pb1200/
cflags-$(CONFIG_MIPS_DB1200) += -Iinclude/asm-mips/mach-db1x00
load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
#
# AMD Alchemy Bosporus eval board
#
......@@ -323,6 +370,7 @@ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
# Cobalt Server
#
core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt
load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
#
......@@ -388,6 +436,13 @@ load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/
load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000
#
# MIPS SIM
#
core-$(CONFIG_MIPS_SIM) += arch/mips/mips-boards/sim/
cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-sim
load-$(CONFIG_MIPS_SIM) += 0x80100000
#
# Momentum Ocelot board
#
......@@ -513,6 +568,19 @@ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
#
load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
#
# Common Philips PNX8550
#
core-$(CONFIG_SOC_PNX8550) += arch/mips/philips/pnx8550/common/
cflags-$(CONFIG_SOC_PNX8550) += -Iinclude/asm-mips/mach-pnx8550
#
# Philips PNX8550 JBS board
#
libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/
#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550
load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
#
# SGI IP22 (Indy/Indigo2)
#
......@@ -582,10 +650,20 @@ load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
# removed (as happens, even if they have __initcall/module_init)
#
core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/
cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte
cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/
cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte
cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte \
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/
cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/
cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
#
# Sibyte BCM91120x (Carmel) board
......@@ -593,6 +671,7 @@ cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte
# Sibyte BCM91125C (CRhone) board
# Sibyte BCM91125E (Rhone) board
# Sibyte SWARM board
# Sibyte BCM91x80 (BigSur) board
#
libs-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/
load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000
......@@ -606,6 +685,8 @@ libs-$(CONFIG_SIBYTE_SENTOSA) += arch/mips/sibyte/swarm/
load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000
libs-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/
load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/
load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
#
# SNI RM200 PCI
......@@ -629,6 +710,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/
core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/
load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000
#
# Toshiba RBTX4938 board
#
core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/
core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/
load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000
cflags-y += -Iinclude/asm-mips/mach-generic
drivers-$(CONFIG_PCI) += arch/mips/pci/
......@@ -701,10 +789,29 @@ ifdef CONFIG_BOOT_ELF64
all: $(vmlinux-64)
endif
ifdef CONFIG_MIPS_ATLAS
all: vmlinux.srec
endif
ifdef CONFIG_MIPS_MALTA
all: vmlinux.srec
endif
ifdef CONFIG_MIPS_SEAD
all: vmlinux.srec
endif
ifdef CONFIG_QEMU
all: vmlinux.bin
endif
ifdef CONFIG_SNI_RM200_PCI
all: vmlinux.ecoff
endif
vmlinux.bin: $(vmlinux-32)
+@$(call makeboot,$@)
vmlinux.ecoff vmlinux.rm200: $(vmlinux-32)
+@$(call makeboot,$@)
......@@ -720,7 +827,6 @@ archclean:
@$(MAKE) $(clean)=arch/mips/boot
@$(MAKE) $(clean)=arch/mips/lasat
CLEAN_FILES += vmlinux.32 \
vmlinux.64 \
vmlinux.ecoff
......@@ -3,7 +3,7 @@
#
lib-y += cmdline.o env.o file.o identify.o init.o \
misc.o time.o tree.o
misc.o salone.o time.o tree.o
lib-$(CONFIG_ARC_MEMORY) += memory.o
lib-$(CONFIG_ARC_CONSOLE) += arc_con.o
......
......@@ -44,6 +44,11 @@ static struct smatch mach_table[] = {
MACH_GROUP_SGI,
MACH_SGI_IP28,
PROM_FLAG_ARCS
}, { "SGI-IP30",
"SGI Octane",
MACH_GROUP_SGI,
MACH_SGI_IP30,
PROM_FLAG_ARCS
}, { "SGI-IP32",
"SGI O2",
MACH_GROUP_SGI,
......
......@@ -8,7 +8,7 @@
obj-y += prom.o int-handler.o irq.o puts.o time.o reset.o \
au1xxx_irqmap.o clocks.o platform.o power.o setup.o \
sleeper.o cputable.o dma.o dbdma.o
sleeper.o cputable.o dma.o dbdma.o gpio.o
obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o
obj-$(CONFIG_KGDB) += dbg_io.o
......
......@@ -173,14 +173,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
{ AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
{ AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
{ AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
{ AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
{ AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
{ AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
{ AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
......@@ -201,14 +201,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = {
{ AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
{ AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
{ AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
{ AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
{ AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
{ AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
{ AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
{ AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
......
......@@ -37,7 +37,8 @@ struct cpu_spec cpu_specs[] = {
{ 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
{ 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
{ 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
{ 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 },
{ 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
{ 0xffffffff, 0x04030201, "Au1200 AC", 0, 1 },
{ 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
};
......
......@@ -29,6 +29,7 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/errno.h>
......@@ -38,10 +39,12 @@
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/system.h>
#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
/*
......@@ -61,37 +64,10 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
*/
#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
static int dbdma_initialized;
static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
static int dbdma_initialized=0;
static void au1xxx_dbdma_init(void);
typedef struct dbdma_device_table {
u32 dev_id;
u32 dev_flags;
u32 dev_tsize;
u32 dev_devwidth;
u32 dev_physaddr; /* If FIFO */
u32 dev_intlevel;
u32 dev_intpolarity;
} dbdev_tab_t;
typedef struct dbdma_chan_config {
u32 chan_flags;
u32 chan_index;
dbdev_tab_t *chan_src;
dbdev_tab_t *chan_dest;
au1x_dma_chan_t *chan_ptr;
au1x_ddma_desc_t *chan_desc_base;
au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
void *chan_callparam;
void (*chan_callback)(int, void *, struct pt_regs *);
} chan_tab_t;
#define DEV_FLAGS_INUSE (1 << 0)
#define DEV_FLAGS_ANYUSE (1 << 1)
#define DEV_FLAGS_OUT (1 << 2)
#define DEV_FLAGS_IN (1 << 3)
static dbdev_tab_t dbdev_tab[] = {
#ifdef CONFIG_SOC_AU1550
/* UARTS */
......@@ -157,25 +133,25 @@ static dbdev_tab_t dbdev_tab[] = {
{ DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
{ DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
{ DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
{ DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
{ DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
{ DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
{ DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
{ DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
{ DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
{ DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
{ DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
{ DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
{ DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
{ DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
{ DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
{ DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
{ DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
{ DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
......@@ -184,6 +160,24 @@ static dbdev_tab_t dbdev_tab[] = {
{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
{ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
/* Provide 16 user definable device types */
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0 },
};
#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
......@@ -203,6 +197,36 @@ find_dbdev_id (u32 id)
return NULL;
}
void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
{
return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
}
EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
u32
au1xxx_ddma_add_device(dbdev_tab_t *dev)
{
u32 ret = 0;
dbdev_tab_t *p=NULL;
static u16 new_id=0x1000;
p = find_dbdev_id(0);
if ( NULL != p )
{
memcpy(p, dev, sizeof(dbdev_tab_t));
p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
ret = p->dev_id;
new_id++;
#if 0
printk("add_device: id:%x flags:%x padd:%x\n",
p->dev_id, p->dev_flags, p->dev_physaddr );
#endif
}
return ret;
}
EXPORT_SYMBOL(au1xxx_ddma_add_device);
/* Allocate a channel and return a non-zero descriptor if successful.
*/
u32
......@@ -215,7 +239,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
int i;
dbdev_tab_t *stp, *dtp;
chan_tab_t *ctp;
volatile au1x_dma_chan_t *cp;
au1x_dma_chan_t *cp;
/* We do the intialization on the first channel allocation.
* We have to wait because of the interrupt handler initialization
......@@ -225,9 +249,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
au1xxx_dbdma_init();
dbdma_initialized = 1;
if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
return 0;
if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
......@@ -271,7 +292,6 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
*/
ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
chan_tab_ptr[i] = ctp;
ctp->chan_index = chan = i;
break;
}
}
......@@ -279,10 +299,11 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
if (ctp != NULL) {
memset(ctp, 0, sizeof(chan_tab_t));
ctp->chan_index = chan = i;
dcp = DDMA_CHANNEL_BASE;
dcp += (0x0100 * chan);
ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
cp = (volatile au1x_dma_chan_t *)dcp;
cp = (au1x_dma_chan_t *)dcp;
ctp->chan_src = stp;
ctp->chan_dest = dtp;
ctp->chan_callback = callback;
......@@ -299,6 +320,9 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
i |= DDMA_CFG_DED;
if (dtp->dev_intpolarity)
i |= DDMA_CFG_DP;
if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
(dtp->dev_flags & DEV_FLAGS_SYNC))
i |= DDMA_CFG_SYNC;
cp->ddma_cfg = i;
au_sync();
......@@ -309,14 +333,14 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
rv = (u32)(&chan_tab_ptr[chan]);
}
else {
/* Release devices.
*/
/* Release devices */
stp->dev_flags &= ~DEV_FLAGS_INUSE;
dtp->dev_flags &= ~DEV_FLAGS_INUSE;
}
}
return rv;
}
EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
/* Set the device width if source or destination is a FIFO.
* Should be 8, 16, or 32 bits.
......@@ -344,6 +368,7 @@ au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
return rv;
}
EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
/* Allocate a descriptor ring, initializing as much as possible.
*/
......@@ -370,7 +395,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
* and if we try that first we are likely to not waste larger
* slabs of memory.
*/
desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL);
desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
GFP_KERNEL|GFP_DMA);
if (desc_base == 0)
return 0;
......@@ -381,7 +407,7 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
kfree((const void *)desc_base);
i = entries * sizeof(au1x_ddma_desc_t);
i += (sizeof(au1x_ddma_desc_t) - 1);
if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0)
if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
return 0;
desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
......@@ -403,7 +429,13 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
cmd0 |= DSCR_CMD0_SID(srcid);
cmd0 |= DSCR_CMD0_DID(destid);
cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_CURRENT);
cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
/* is it mem to mem transfer? */
if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) {
cmd0 |= DSCR_CMD0_MEM;
}
switch (stp->dev_devwidth) {
case 8:
......@@ -461,9 +493,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
/* If source input is fifo, set static address.
*/
if (stp->dev_flags & DEV_FLAGS_IN) {
src0 = stp->dev_physaddr;
if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
else
src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
}
if (stp->dev_physaddr)
src0 = stp->dev_physaddr;
/* Set up dest1. For now, assume no stride and increment.
* A channel attribute update can change this later.
......@@ -487,10 +524,18 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
/* If destination output is fifo, set static address.
*/
if (dtp->dev_flags & DEV_FLAGS_OUT) {
dest0 = dtp->dev_physaddr;
if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
else
dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
}
if (dtp->dev_physaddr)
dest0 = dtp->dev_physaddr;
#if 0
printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
#endif
for (i=0; i<entries; i++) {
dp->dscr_cmd0 = cmd0;
dp->dscr_cmd1 = cmd1;
......@@ -499,6 +544,8 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
dp->dscr_dest0 = dest0;
dp->dscr_dest1 = dest1;
dp->dscr_stat = 0;
dp->sw_context = 0;
dp->sw_status = 0;
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
dp++;
}
......@@ -511,13 +558,14 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
return (u32)(ctp->chan_desc_base);
}
EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
/* Put a source buffer into the DMA ring.
* This updates the source pointer and byte count. Normally used
* for memory to fifo transfers.
*/
u32
au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
......@@ -544,8 +592,24 @@ au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
*/
dp->dscr_source0 = virt_to_phys(buf);
dp->dscr_cmd1 = nbytes;
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */
/* Check flags */
if (flags & DDMA_FLAGS_IE)
dp->dscr_cmd0 |= DSCR_CMD0_IE;
if (flags & DDMA_FLAGS_NOIE)
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
/*
* There is an errata on the Au1200/Au1550 parts that could result
* in "stale" data being DMA'd. It has to do with the snoop logic on
* the dache eviction buffer. NONCOHERENT_IO is on by default for
* these parts. If it is fixedin the future, these dma_cache_inv will
* just be nothing more than empty macros. See io.h.
* */
dma_cache_wback_inv((unsigned long)buf, nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
au_sync();
dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer.
*/
......@@ -555,13 +619,14 @@ au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
*/
return nbytes;
}
EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
/* Put a destination buffer into the DMA ring.
* This updates the destination pointer and byte count. Normally used
* to place an empty buffer into the ring for fifo to memory transfers.
*/
u32
au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
......@@ -583,11 +648,33 @@ au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Load up buffer address and byte count.
*/
/* Load up buffer address and byte count */
/* Check flags */
if (flags & DDMA_FLAGS_IE)
dp->dscr_cmd0 |= DSCR_CMD0_IE;
if (flags & DDMA_FLAGS_NOIE)
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
dp->dscr_dest0 = virt_to_phys(buf);
dp->dscr_cmd1 = nbytes;
#if 0
printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
#endif
/*
* There is an errata on the Au1200/Au1550 parts that could result in
* "stale" data being DMA'd. It has to do with the snoop logic on the
* dache eviction buffer. NONCOHERENT_IO is on by default for these
* parts. If it is fixedin the future, these dma_cache_inv will just
* be nothing more than empty macros. See io.h.
* */
dma_cache_inv((unsigned long)buf,nbytes);
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
au_sync();
dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer.
*/
......@@ -597,6 +684,7 @@ au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
*/
return nbytes;
}
EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
/* Get a destination buffer into the DMA ring.
* Normally used to get a full buffer from the ring during fifo
......@@ -646,7 +734,7 @@ void
au1xxx_dbdma_stop(u32 chanid)
{
chan_tab_t *ctp;
volatile au1x_dma_chan_t *cp;
au1x_dma_chan_t *cp;
int halt_timeout = 0;
ctp = *((chan_tab_t **)chanid);
......@@ -666,6 +754,7 @@ au1xxx_dbdma_stop(u32 chanid)
cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
au_sync();
}
EXPORT_SYMBOL(au1xxx_dbdma_stop);
/* Start using the current descriptor pointer. If the dbdma encounters
* a not valid descriptor, it will stop. In this case, we can just
......@@ -675,17 +764,17 @@ void
au1xxx_dbdma_start(u32 chanid)
{
chan_tab_t *ctp;
volatile au1x_dma_chan_t *cp;
au1x_dma_chan_t *cp;
ctp = *((chan_tab_t **)chanid);
cp = ctp->chan_ptr;
cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
au_sync();
cp->ddma_dbell = 0xffffffff; /* Make it go */
cp->ddma_dbell = 0;
au_sync();
}
EXPORT_SYMBOL(au1xxx_dbdma_start);
void
au1xxx_dbdma_reset(u32 chanid)
......@@ -704,15 +793,21 @@ au1xxx_dbdma_reset(u32 chanid)
do {
dp->dscr_cmd0 &= ~DSCR_CMD0_V;
/* reset our SW status -- this is used to determine
* if a descriptor is in use by upper level SW. Since
* posting can reset 'V' bit.
*/
dp->sw_status = 0;
dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
} while (dp != ctp->chan_desc_base);
}
EXPORT_SYMBOL(au1xxx_dbdma_reset);
u32
au1xxx_get_dma_residue(u32 chanid)
{
chan_tab_t *ctp;
volatile au1x_dma_chan_t *cp;
au1x_dma_chan_t *cp;
u32 rv;
ctp = *((chan_tab_t **)chanid);
......@@ -738,8 +833,7 @@ au1xxx_dbdma_chan_free(u32 chanid)
au1xxx_dbdma_stop(chanid);
if (ctp->chan_desc_base != NULL)
kfree(ctp->chan_desc_base);
kfree((void *)ctp->chan_desc_base);
stp->dev_flags &= ~DEV_FLAGS_INUSE;
dtp->dev_flags &= ~DEV_FLAGS_INUSE;
......@@ -747,15 +841,16 @@ au1xxx_dbdma_chan_free(u32 chanid)
kfree(ctp);
}
EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
static irqreturn_t
dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
u32 intstat;
u32 chan_index;
u32 intstat;
u32 chan_index;
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
volatile au1x_dma_chan_t *cp;
au1x_dma_chan_t *cp;
intstat = dbdma_gptr->ddma_intstat;
au_sync();
......@@ -774,19 +869,27 @@ dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
(ctp->chan_callback)(irq, ctp->chan_callparam, regs);
ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
return IRQ_HANDLED;
return IRQ_RETVAL(1);
}
static void
au1xxx_dbdma_init(void)
static void au1xxx_dbdma_init(void)
{
int irq_nr;
dbdma_gptr->ddma_config = 0;
dbdma_gptr->ddma_throttle = 0;
dbdma_gptr->ddma_inten = 0xffff;
au_sync();
if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT,
#if defined(CONFIG_SOC_AU1550)
irq_nr = AU1550_DDMA_INT;
#elif defined(CONFIG_SOC_AU1200)
irq_nr = AU1200_DDMA_INT;
#else
#error Unknown Au1x00 SOC
#endif
if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
"Au1xxx dbdma", (void *)dbdma_gptr))
printk("Can't get 1550 dbdma irq");
}
......@@ -797,7 +900,8 @@ au1xxx_dbdma_dump(u32 chanid)
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
dbdev_tab_t *stp, *dtp;
volatile au1x_dma_chan_t *cp;
au1x_dma_chan_t *cp;
u32 i = 0;
ctp = *((chan_tab_t **)chanid);
stp = ctp->chan_src;
......@@ -822,15 +926,64 @@ au1xxx_dbdma_dump(u32 chanid)
dp = ctp->chan_desc_base;
do {
printk("dp %08x, cmd0 %08x, cmd1 %08x\n",
(u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
printk("src0 %08x, src1 %08x, dest0 %08x\n",
dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0);
printk("dest1 %08x, stat %08x, nxtptr %08x\n",
dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr);
printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
printk("stat %08x, nxtptr %08x\n",
dp->dscr_stat, dp->dscr_nxtptr);
dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
} while (dp != ctp->chan_desc_base);
}
/* Put a descriptor into the DMA ring.
* This updates the source/destination pointers and byte count.
*/
u32
au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
{
chan_tab_t *ctp;
au1x_ddma_desc_t *dp;
u32 nbytes=0;
/* I guess we could check this to be within the
* range of the table......
*/
ctp = *((chan_tab_t **)chanid);
/* We should have multiple callers for a particular channel,
* an interrupt doesn't affect this pointer nor the descriptor,
* so no locking should be needed.
*/
dp = ctp->put_ptr;
/* If the descriptor is valid, we are way ahead of the DMA
* engine, so just return an error condition.
*/
if (dp->dscr_cmd0 & DSCR_CMD0_V)
return 0;
/* Load up buffer addresses and byte count.
*/
dp->dscr_dest0 = dscr->dscr_dest0;
dp->dscr_source0 = dscr->dscr_source0;
dp->dscr_dest1 = dscr->dscr_dest1;
dp->dscr_source1 = dscr->dscr_source1;
dp->dscr_cmd1 = dscr->dscr_cmd1;
nbytes = dscr->dscr_cmd1;
/* Allow the caller to specifiy if an interrupt is generated */
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
ctp->chan_ptr->ddma_dbell = 0;
/* Get next descriptor pointer.
*/
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
/* return something not zero.
*/
return nbytes;
}
#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
......@@ -39,7 +39,6 @@
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/system.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
......
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <au1000.h>
#include <au1xxx_gpio.h>
#define gpio1 sys
#if !defined(CONFIG_SOC_AU1000)
static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE;
#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
int au1xxx_gpio2_read(int signal)
{
signal -= 200;
/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */
return ((gpio2->pinstate >> signal) & 0x01);
}
void au1xxx_gpio2_write(int signal, int value)
{
signal -= 200;
gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) |
(value << signal);
}
void au1xxx_gpio2_tristate(int signal)
{
signal -= 200;
gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */
}
#endif
int au1xxx_gpio1_read(int signal)
{
/* gpio1->trioutclr |= (0x01 << signal); */
return ((gpio1->pinstaterd >> signal) & 0x01);
}
void au1xxx_gpio1_write(int signal, int value)
{
if(value)
gpio1->outputset = (0x01 << signal);
else
gpio1->outputclr = (0x01 << signal); /* Output a Zero */
}
void au1xxx_gpio1_tristate(int signal)
{
gpio1->trioutclr = (0x01 << signal); /* Tristate signal */
}
int au1xxx_gpio_read(int signal)
{
if(signal >= 200)
#if defined(CONFIG_SOC_AU1000)
return 0;
#else
return au1xxx_gpio2_read(signal);
#endif
else
return au1xxx_gpio1_read(signal);
}
void au1xxx_gpio_write(int signal, int value)
{
if(signal >= 200)
#if defined(CONFIG_SOC_AU1000)
;
#else
au1xxx_gpio2_write(signal, value);
#endif
else
au1xxx_gpio1_write(signal, value);
}
void au1xxx_gpio_tristate(int signal)
{
if(signal >= 200)
#if defined(CONFIG_SOC_AU1000)
;
#else
au1xxx_gpio2_tristate(signal);
#endif
else
au1xxx_gpio1_tristate(signal);
}
void au1xxx_gpio1_set_inputs(void)
{
gpio1->pininputen = 0;
}
EXPORT_SYMBOL(au1xxx_gpio1_set_inputs);
EXPORT_SYMBOL(au1xxx_gpio_tristate);
EXPORT_SYMBOL(au1xxx_gpio_write);
EXPORT_SYMBOL(au1xxx_gpio_read);
......@@ -83,7 +83,7 @@ inline void local_disable_irq(unsigned int irq_nr);
void (*board_init_irq)(void);
#ifdef CONFIG_PM
extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
extern irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
#endif
static DEFINE_SPINLOCK(irq_lock);
......@@ -253,52 +253,72 @@ void restore_local_and_enable(int controller, unsigned long mask)
static struct hw_interrupt_type rise_edge_irq_type = {
"Au1000 Rise Edge",
startup_irq,
shutdown_irq,
local_enable_irq,
local_disable_irq,
mask_and_ack_rise_edge_irq,
end_irq,
NULL
.typename = "Au1000 Rise Edge",
.startup = startup_irq,
.shutdown = shutdown_irq,
.enable = local_enable_irq,
.disable = local_disable_irq,
.ack = mask_and_ack_rise_edge_irq,
.end = end_irq,
};
static struct hw_interrupt_type fall_edge_irq_type = {
"Au1000 Fall Edge",
startup_irq,
shutdown_irq,
local_enable_irq,
local_disable_irq,
mask_and_ack_fall_edge_irq,
end_irq,
NULL
.typename = "Au1000 Fall Edge",
.startup = startup_irq,
.shutdown = shutdown_irq,
.enable = local_enable_irq,
.disable = local_disable_irq,
.ack = mask_and_ack_fall_edge_irq,
.end = end_irq,
};
static struct hw_interrupt_type either_edge_irq_type = {
"Au1000 Rise or Fall Edge",
startup_irq,
shutdown_irq,
local_enable_irq,
local_disable_irq,
mask_and_ack_either_edge_irq,
end_irq,
NULL
.typename = "Au1000 Rise or Fall Edge",
.startup = startup_irq,
.shutdown = shutdown_irq,
.enable = local_enable_irq,
.disable = local_disable_irq,
.ack = mask_and_ack_either_edge_irq,
.end = end_irq,
};
static struct hw_interrupt_type level_irq_type = {
"Au1000 Level",
startup_irq,
shutdown_irq,
local_enable_irq,
local_disable_irq,
mask_and_ack_level_irq,
end_irq,
NULL
.typename = "Au1000 Level",
.startup = startup_irq,
.shutdown = shutdown_irq,
.enable = local_enable_irq,
.disable = local_disable_irq,
.ack = mask_and_ack_level_irq,
.end = end_irq,
};
#ifdef CONFIG_PM
void startup_match20_interrupt(void)
void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *))
{
struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
static struct irqaction action;
memset(&action, 0, sizeof(struct irqaction));
/* This is a big problem.... since we didn't use request_irq
* when kernel/irq.c calls probe_irq_xxx this interrupt will
* be probed for usage. This will end up disabling the device :(
* Give it a bogus "action" pointer -- this will keep it from
* getting auto-probed!
*
* By setting the status to match that of request_irq() we
* can avoid it. --cgray
*/
action.dev_id = handler;
action.flags = SA_INTERRUPT;
cpus_clear(action.mask);
action.name = "Au1xxx TOY";
action.handler = handler;
action.next = NULL;
desc->action = &action;
desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
local_enable_irq(AU1000_TOY_MATCH2_INT);
}
#endif
......@@ -426,7 +446,6 @@ void __init arch_init_irq(void)
extern int au1xxx_ic0_nr_irqs;
cp0_status = read_c0_status();
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, au1000_IRQ);
/* Initialize interrupt controllers to a safe state.
......@@ -492,7 +511,7 @@ void intc0_req0_irqdispatch(struct pt_regs *regs)
intc0_req0 |= au_readl(IC0_REQ0INT);
if (!intc0_req0) return;
#ifdef AU1000_USB_DEV_REQ_INT
/*
* Because of the tight timing of SETUP token to reply
* transactions, the USB devices-side packet complete
......@@ -503,7 +522,7 @@ void intc0_req0_irqdispatch(struct pt_regs *regs)
do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
return;
}
#endif
irq = au_ffs(intc0_req0) - 1;
intc0_req0 &= ~(1<<irq);
do_IRQ(irq, regs);
......@@ -521,17 +540,7 @@ void intc0_req1_irqdispatch(struct pt_regs *regs)
irq = au_ffs(intc0_req1) - 1;
intc0_req1 &= ~(1<<irq);
#ifdef CONFIG_PM
if (irq == AU1000_TOY_MATCH2_INT) {
mask_and_ack_rise_edge_irq(irq);
counter0_irq(irq, NULL, regs);
local_enable_irq(irq);
}
else
#endif
{
do_IRQ(irq, regs);
}
do_IRQ(irq, regs);
}
......
......@@ -7,13 +7,15 @@
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/config.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/resource.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx.h>
/* OHCI (USB full speed host controller) */
static struct resource au1xxx_usb_ohci_resources[] = {
[0] = {
.start = USB_OHCI_BASE,
......@@ -41,8 +43,252 @@ static struct platform_device au1xxx_usb_ohci_device = {
.resource = au1xxx_usb_ohci_resources,
};
/*** AU1100 LCD controller ***/
#ifdef CONFIG_FB_AU1100
static struct resource au1100_lcd_resources[] = {
[0] = {
.start = LCD_PHYS_ADDR,
.end = LCD_PHYS_ADDR + 0x800 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1100_LCD_INT,
.end = AU1100_LCD_INT,
.flags = IORESOURCE_IRQ,
}
};
static u64 au1100_lcd_dmamask = ~(u32)0;
static struct platform_device au1100_lcd_device = {
.name = "au1100-lcd",
.id = 0,
.dev = {
.dma_mask = &au1100_lcd_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(au1100_lcd_resources),
.resource = au1100_lcd_resources,
};
#endif
#ifdef CONFIG_SOC_AU1200
/* EHCI (USB high speed host controller) */
static struct resource au1xxx_usb_ehci_resources[] = {
[0] = {
.start = USB_EHCI_BASE,
.end = USB_EHCI_BASE + USB_EHCI_LEN - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1000_USB_HOST_INT,
.end = AU1000_USB_HOST_INT,
.flags = IORESOURCE_IRQ,
},
};
static u64 ehci_dmamask = ~(u32)0;
static struct platform_device au1xxx_usb_ehci_device = {
.name = "au1xxx-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
.resource = au1xxx_usb_ehci_resources,
};
/* Au1200 UDC (USB gadget controller) */
static struct resource au1xxx_usb_gdt_resources[] = {
[0] = {
.start = USB_UDC_BASE,
.end = USB_UDC_BASE + USB_UDC_LEN - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_USB_INT,
.end = AU1200_USB_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct resource au1xxx_mmc_resources[] = {
[0] = {
.start = SD0_PHYS_ADDR,
.end = SD0_PHYS_ADDR + 0x40,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SD1_PHYS_ADDR,
.end = SD1_PHYS_ADDR + 0x40,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = AU1200_SD_INT,
.end = AU1200_SD_INT,
.flags = IORESOURCE_IRQ,
}
};
static u64 udc_dmamask = ~(u32)0;
static struct platform_device au1xxx_usb_gdt_device = {
.name = "au1xxx-udc",
.id = 0,
.dev = {
.dma_mask = &udc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
.resource = au1xxx_usb_gdt_resources,
};
/* Au1200 UOC (USB OTG controller) */
static struct resource au1xxx_usb_otg_resources[] = {
[0] = {
.start = USB_UOC_BASE,
.end = USB_UOC_BASE + USB_UOC_LEN - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_USB_INT,
.end = AU1200_USB_INT,
.flags = IORESOURCE_IRQ,
},
};
static u64 uoc_dmamask = ~(u32)0;
static struct platform_device au1xxx_usb_otg_device = {
.name = "au1xxx-uoc",
.id = 0,
.dev = {
.dma_mask = &uoc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
.resource = au1xxx_usb_otg_resources,
};
static struct resource au1200_lcd_resources[] = {
[0] = {
.start = LCD_PHYS_ADDR,
.end = LCD_PHYS_ADDR + 0x800 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1200_LCD_INT,
.end = AU1200_LCD_INT,
.flags = IORESOURCE_IRQ,
}
};
static struct resource au1200_ide0_resources[] = {
[0] = {
.start = AU1XXX_ATA_PHYS_ADDR,
.end = AU1XXX_ATA_PHYS_ADDR + AU1XXX_ATA_PHYS_LEN,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1XXX_ATA_INT,
.end = AU1XXX_ATA_INT,
.flags = IORESOURCE_IRQ,
}
};
static u64 au1200_lcd_dmamask = ~(u32)0;
static struct platform_device au1200_lcd_device = {
.name = "au1200-lcd",
.id = 0,
.dev = {
.dma_mask = &au1200_lcd_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(au1200_lcd_resources),
.resource = au1200_lcd_resources,
};
static u64 ide0_dmamask = ~(u32)0;
static struct platform_device au1200_ide0_device = {
.name = "au1200-ide",
.id = 0,
.dev = {
.dma_mask = &ide0_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(au1200_ide0_resources),
.resource = au1200_ide0_resources,
};
static u64 au1xxx_mmc_dmamask = ~(u32)0;
static struct platform_device au1xxx_mmc_device = {
.name = "au1xxx-mmc",
.id = 0,
.dev = {
.dma_mask = &au1xxx_mmc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(au1xxx_mmc_resources),
.resource = au1xxx_mmc_resources,
};
#endif /* #ifdef CONFIG_SOC_AU1200 */
static struct platform_device au1x00_pcmcia_device = {
.name = "au1x00-pcmcia",
.id = 0,
};
#ifdef CONFIG_MIPS_DB1200
static struct resource smc91x_resources[] = {
[0] = {
.name = "smc91x-regs",
.start = AU1XXX_SMC91111_PHYS_ADDR,
.end = AU1XXX_SMC91111_PHYS_ADDR + 0xfffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AU1XXX_SMC91111_IRQ,
.end = AU1XXX_SMC91111_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
#endif
static struct platform_device *au1xxx_platform_devices[] __initdata = {
&au1xxx_usb_ohci_device,
&au1x00_pcmcia_device,
#ifdef CONFIG_FB_AU1100
&au1100_lcd_device,
#endif
#ifdef CONFIG_SOC_AU1200
#if 0 /* fixme */
&au1xxx_usb_ehci_device,
#endif
&au1xxx_usb_gdt_device,
&au1xxx_usb_otg_device,
&au1200_lcd_device,
&au1200_ide0_device,
&au1xxx_mmc_device,
#endif
#ifdef CONFIG_MIPS_DB1200
&smc91x_device,
#endif
};
int au1xxx_platform_init(void)
......
......@@ -34,11 +34,13 @@
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/sysctl.h>
#include <linux/jiffies.h>
#include <asm/string.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/cacheflush.h>
#include <asm/mach-au1x00/au1000.h>
#ifdef CONFIG_PM
......@@ -50,7 +52,7 @@
# define DPRINTK(fmt, args...)
#endif
static void calibrate_delay(void);
static void au1000_calibrate_delay(void);
extern void set_au1x00_speed(unsigned int new_freq);
extern unsigned int get_au1x00_speed(void);
......@@ -260,7 +262,7 @@ int au_sleep(void)
}
static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
void *buffer, size_t * len)
void __user *buffer, size_t * len, loff_t *ppos)
{
int retval = 0;
#ifdef SLEEP_TEST_TIMEOUT
......@@ -294,10 +296,9 @@ static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
}
static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
void *buffer, size_t * len)
void __user *buffer, size_t * len, loff_t *ppos)
{
int retval = 0;
void au1k_wait(void);
if (!write) {
*len = 0;
......@@ -306,7 +307,7 @@ static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
if (retval)
return retval;
suspend_mode = 1;
au1k_wait();
retval = pm_send_all(PM_RESUME, (void *) 0);
}
return retval;
......@@ -314,7 +315,7 @@ static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
void *buffer, size_t * len)
void __user *buffer, size_t * len, loff_t *ppos)
{
int retval = 0, i;
unsigned long val, pll;
......@@ -409,14 +410,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
/* We don't want _any_ interrupts other than
* match20. Otherwise our calibrate_delay()
* match20. Otherwise our au1000_calibrate_delay()
* calculation will be off, potentially a lot.
*/
intc0_mask = save_local_and_disable(0);
intc1_mask = save_local_and_disable(1);
local_enable_irq(AU1000_TOY_MATCH2_INT);
spin_unlock_irqrestore(&pm_lock, flags);
calibrate_delay();
au1000_calibrate_delay();
restore_local_and_enable(0, intc0_mask);
restore_local_and_enable(1, intc1_mask);
return retval;
......@@ -456,7 +457,7 @@ __initcall(pm_init);
better than 1% */
#define LPS_PREC 8
static void calibrate_delay(void)
static void au1000_calibrate_delay(void)
{
unsigned long ticks, loopbit;
int lps_precision = LPS_PREC;
......
......@@ -75,7 +75,8 @@ void prom_init_cmdline(void)
}
if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
--cp;
*cp = '\0';
if (prom_argc > 1)
*cp = '\0';
}
......
......@@ -39,7 +39,6 @@
#define TIMEOUT 0xffffff
#define SLOW_DOWN
static const char digits[16] = "0123456789abcdef";
static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE;
......@@ -54,7 +53,7 @@ static inline void slow_down(void)
#endif
void
putch(const unsigned char c)
prom_putchar(const unsigned char c)
{
unsigned char ch;
int i = 0;
......@@ -69,77 +68,3 @@ putch(const unsigned char c)
} while (0 == (ch & TX_BUSY));
com1[SER_DATA] = c;
}
void
puts(unsigned char *cp)
{
unsigned char ch;
int i = 0;
while (*cp) {
do {
ch = com1[SER_CMD];
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
com1[SER_DATA] = *cp++;
}
putch('\r');
putch('\n');
}
void
fputs(const char *cp)
{
unsigned char ch;
int i = 0;
while (*cp) {
do {
ch = com1[SER_CMD];
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
com1[SER_DATA] = *cp++;
}
}
void
put64(uint64_t ul)
{
int cnt;
unsigned ch;
cnt = 16; /* 16 nibbles in a 64 bit long */
putch('0');
putch('x');
do {
cnt--;
ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
putch(digits[ch]);
} while (cnt > 0);
}
void
put32(unsigned u)
{
int cnt;
unsigned ch;
cnt = 8; /* 8 nibbles in a 32 bit long */
putch('0');
putch('x');
do {
cnt--;
ch = (unsigned char)(u >> cnt * 4) & 0x0F;
putch(digits[ch]);
} while (cnt > 0);
}
......@@ -32,6 +32,7 @@
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
......@@ -57,7 +58,7 @@ extern void au1xxx_time_init(void);
extern void au1xxx_timer_setup(struct irqaction *irq);
extern void set_cpuspec(void);
static int __init au1x00_setup(void)
void __init plat_setup(void)
{
struct cpu_spec *sp;
char *argptr;
......@@ -106,8 +107,6 @@ static int __init au1x00_setup(void)
/*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
#ifdef CONFIG_MIPS_HYDROGEN3
strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
#else
strcat(argptr, " video=au1100fb:panel:s10,nohwcursor");
#endif
}
#endif
......@@ -153,15 +152,11 @@ static int __init au1x00_setup(void)
au_sync();
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
au_writel(0, SYS_TOYTRIM);
return 0;
}
early_initcall(au1x00_setup);
#if defined(CONFIG_64BIT_PHYS_ADDR)
/* This routine should be valid for all Au1x based boards */
phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
u32 start, end;
......@@ -192,4 +187,5 @@ phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
/* default nop */
return phys_addr;
}
EXPORT_SYMBOL(__fixup_bigphys_addr);
#endif
......@@ -50,7 +50,6 @@
#include <linux/mc146818rtc.h>
#include <linux/timex.h>
extern void startup_match20_interrupt(void);
extern void do_softirq(void);
extern volatile unsigned long wall_jiffies;
unsigned long missed_heart_beats = 0;
......@@ -58,14 +57,17 @@ unsigned long missed_heart_beats = 0;
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
int no_au1xxx_32khz;
void (*au1k_wait_ptr)(void);
extern int allow_au1k_wait; /* default off for CP0 Counter */
/* Cycle counter value at the previous timer interrupt.. */
static unsigned int timerhi = 0, timerlo = 0;
#ifdef CONFIG_PM
#define MATCH20_INC 328
extern void startup_match20_interrupt(void);
#if HZ < 100 || HZ > 1000
#error "unsupported HZ value! Must be in [100,1000]"
#endif
#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
extern void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *));
static unsigned long last_pc0, last_match20;
#endif
......@@ -117,17 +119,16 @@ void mips_timer_interrupt(struct pt_regs *regs)
}
#ifdef CONFIG_PM
void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned long pc0;
int time_elapsed;
static int jiffie_drift = 0;
kstat.irqs[0][irq]++;
if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
/* should never happen! */
printk(KERN_WARNING "counter 0 w status eror\n");
return;
printk(KERN_WARNING "counter 0 w status error\n");
return IRQ_NONE;
}
pc0 = au_readl(SYS_TOYREAD);
......@@ -164,6 +165,8 @@ void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
update_process_times(user_mode(regs));
#endif
}
return IRQ_HANDLED;
}
/* When we wakeup from sleep, we have to "catch up" on all of the
......@@ -388,7 +391,6 @@ void au1xxx_timer_setup(struct irqaction *irq)
{
unsigned int est_freq;
extern unsigned long (*do_gettimeoffset)(void);
extern void au1k_wait(void);
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
......@@ -441,18 +443,18 @@ void au1xxx_timer_setup(struct irqaction *irq)
au_sync();
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
/* setup match20 to interrupt once every 10ms */
/* setup match20 to interrupt once every HZ */
last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
au_sync();
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
startup_match20_interrupt();
startup_match20_interrupt(counter0_irq);
do_gettimeoffset = do_fast_pm_gettimeoffset;
/* We can use the real 'wait' instruction.
*/
au1k_wait_ptr = au1k_wait;
allow_au1k_wait = 1;
}
#else
......
......@@ -1005,11 +1005,11 @@ process_ep0_receive (struct usb_dev* dev)
#endif
dev->ep0_stage = SETUP_STAGE;
break;
}
}
spin_unlock(&ep0->lock);
// we're done processing the packet, free it
kfree(pkt);
// we're done processing the packet, free it
kfree(pkt);
}
......@@ -1072,8 +1072,7 @@ dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs)
clear_dma_done1(ep0->indma);
pkt = send_packet_complete(ep0);
if (pkt)
kfree(pkt);
kfree(pkt);
}
/*
......@@ -1302,8 +1301,7 @@ usbdev_exit(void)
endpoint_flush(ep);
}
if (usbdev.full_conf_desc)
kfree(usbdev.full_conf_desc);
kfree(usbdev.full_conf_desc);
}
int
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment