-
Paul Mackerras authored
I had the codes for L1 D-cache load accesses and misses swapped around, and the wrong codes for LL-cache accesses and misses. This corrects them. Reported-by:
Corey Ashford <cjashfor@linux.vnet.ibm.com>
Signed-off-by:
Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: <stable@kernel.org>
LKML-Reference: <19103.8514.709300.585484@cargo.ozlabs.ibm.com>
Signed-off-by:
Ingo Molnar <mingo@elte.hu>a3df6f7d