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Report by Jody McIntyre. Thanks!

Corresponding to flashrom svn r388 and coreboot v2 svn r3893.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Report by Scaldov M.V. Thanks!

Corresponding to flashrom svn r387 and coreboot v2 svn r3892.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r386 and coreboot v2 svn r3890.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Resolves #121

Corresponding to flashrom svn r385 and coreboot v2 svn r3889.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r384 and coreboot v2 svn r3869.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>

Corresponding to flashrom svn r383 and coreboot v2 svn r3862.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Similarly to flashchips array, this patch intends to make the table board_pciid_enables more readable.

Corresponding to flashrom svn r382 and coreboot v2 svn r3861.
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>

> What real problem does this solve?

1. Next time someone adds a new struct member, we avoid mistakes of
ordering of initializers
2. we avoid mistakes in the first place.

The .x = y stuff was added for a (good) reason, I think this is an
improvement.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r381 and coreboot v2 svn r3860.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge.
The board uses GIGABYTE's patented BIOS failover technology, and at this point
we do not know how to control which of the two chips flashrom actually hits.

Corresponding to flashrom svn r380 and coreboot v2 svn r3859.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>

Corresponding to flashrom svn r379 and coreboot v2 svn r3858.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>

Fix build error on distros with warn_unused_result attributes in glibc.

Corresponding to flashrom svn r378 and coreboot v2 svn r3857.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>

Mimicked from flashrom.c

Corresponding to flashrom svn r377 and coreboot v2 svn r3855.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>

AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641
AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321
AT26F004

Straight from the data sheets, untested because I lack the hardware.

Corresponding to flashrom svn r376 and coreboot v2 svn r3853.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

- Remove the copyright listings and refer the reader to the source
  files.
- Update the author list to those which have copyright messages in the
source files.
- Correct the license from GPL v2+ to (GPL v2, with some files under
  later versions as well)

Corresponding to flashrom svn r375 and coreboot v2 svn r3852.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

The explicit initialization makes sure any future struct flashchip
reordering is not needed. (Except for the case where we need arrays
of some of the struct members.)

Corresponding to flashrom svn r374 and coreboot v2 svn r3851.
Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux@free.fr>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r373 and coreboot v2 svn r3850.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r372 and coreboot v2 svn r3849.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r371 and coreboot v2 svn r3848.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Fix that by throwing an error instead.

Corresponding to flashrom svn r370 and coreboot v2 svn r3834.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

There seem to be at least two versions of the board out there, and the
subsystem IDs changed between the versions.

Patch successfully tested on hardware.

Corresponding to flashrom svn r369 and coreboot v2 svn r3833.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r368 and coreboot v2 svn r3830.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

* add a generic preop-opcode-pair table.

* rename ich_check_opcodes to ich_init_opcodes.

* let ich_init_opcodes do not need to access flashchip structure:
  . move the definition of struct preop_opcode_pair to a better place
  . remove preop_opcode_pairs from 'struct flashchip'
  . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure

* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.

* fix a coding style mistake.

Corresponding to flashrom svn r367 and coreboot v2 svn r3814.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>

MX29LV040C probe and read support tested by khetzal on IRC.

Corresponding to flashrom svn r366 and coreboot v2 svn r3809.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r365 and coreboot v2 svn r3806.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r364 and coreboot v2 svn r3805.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Corresponding to flashrom svn r363 and coreboot v2 svn r3804.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Looks like this:

Supported flash chips:          Tested OK operations:   Known BAD operations:

AMD Am29F002(N)BB                                       
AMD Am29F002(N)BT               PROBE READ ERASE WRITE  
AMD Am29F016D                                           
AMD Am29F040B                   PROBE READ ERASE WRITE  
AMD Am29LV040B                                          
Atmel AT45CS1282                                        READ 

Corresponding to flashrom svn r362 and coreboot v2 svn r3803.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

This patch adds SB700 support to flashrom. The code for enabling the flash
rom is the same as for SB600. It was tested (read, write, verify) with an
ASUS M3A-H/HDMI which contains a Macronix MX25L8005.

Corresponding to flashrom svn r361 and coreboot v2 svn r3799.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Peter Stuge <peter@stuge.se>

Thanks to Niels Ole Salscheider for the problem report.

Corresponding to flashrom svn r360 and coreboot v2 svn r3798.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Flashrom used to exit 0 even if erase failed. Not anymore.

Corresponding to flashrom svn r359 and coreboot v2 svn r3797.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

SST_25VF512A_REMS
SST_25VF010_REMS
SST_25VF020_REMS
SST_25VF040_REMS
SST_25VF040B_REMS
SST_25VF080_REMS
SST_25VF080B_REMS
SST_25VF032B_REMS
SST_26VF016
SST_26VF032
W_25X16
W_25X32
W_25X64

Straight from the data sheets.

The REMS IDs help in case the RDID opcode is unavailable (due to opcode
lockdown) or unsupported by the chip.

Some day, we need to pair probe functions together with IDs. Multiple
pairs can exist per chip and duplicating chip definitions does not
really make sense.

Corresponding to flashrom svn r358 and coreboot v2 svn r3793.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Bug from r3791.

Corresponding to flashrom svn r357 and coreboot v2 svn r3792.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

If flashbase was set before probe_flash() it would only ever be used once, for
the very first flash chip probe.

Corresponding to flashrom svn r356 and coreboot v2 svn r3791.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Fixes #109

Corresponding to flashrom svn r355 and coreboot v2 svn r3790.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Corresponding to flashrom svn r354 and coreboot v2 svn r3782.
Signed-off-by: Jason Wang <Qingpei.wang@amd.com>
Reviewed-by: Joe, Bao <Zheng.Bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Corresponding to flashrom svn r353 and coreboot v2 svn r3781.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

If a chip has any TEST_BAD_* flag set, we don't even list the
unsupported functions, giving the user the impression that the
unsupported functions are tested.

Corresponding to flashrom svn r352 and coreboot v2 svn r3780.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

This has been tested by Uwe Hermann on an RS690/SB600 board.

Corresponding to flashrom svn r351 and coreboot v2 svn r3779.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

This is the first chip which uses the infrastructure for alternative
erase commands, namely spi_chip_erase_60_c7().

Corresponding to flashrom svn r350 and coreboot v2 svn r3776.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID

RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.

The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES

Corresponding to flashrom svn r349 and coreboot v2 svn r3775.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>