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  1. 13 Oct, 2010 2 commits
  3. 10 Oct, 2010 2 commits
    • Carl-Daniel Hailfinger's avatar
      Simplify calls to inner write functions · 184b95f4
      Carl-Daniel Hailfinger authored 
      
No behavioural changes, just equivalence transformations.

Corresponding to flashrom svn r1209.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      184b95f4
    • Carl-Daniel Hailfinger's avatar
      Unify chip write functions · b30a5ed4
      Carl-Daniel Hailfinger authored 
      
The currently used write functions (wrappers) all use helpers which
perform the actual write (inner functions).

The signature of the write wrappers is: int write_chip(struct flashchip
*flash, uint8_t * buf);

The signature of the inner write functions varied a lot. This patch
changes them to: int write_part(struct flashchip *flash, uint8_t *src,
int start, int len);

Did you know that flashrom has only 8 inner write functions for all
flash chips? write_page_write_jedec_common write_sector_jedec_common
write_sector_28sf040 spi_chip_write_256_new spi_chip_write_1_new
spi_aai_write_new write_page_82802ab write_page_m29f400bt

Export all inner write functions.

Change the function signature of wait_82802ab to eliminate single-use
variables.

Remove an error message in write_page_m29f400bt which was printed for
every byte written regardless of success.

Add sharplhf00l04.c to the list of flash chip drivers in the Makefile.
While the functions in there are unused, I suspect we will need them
later, and by hooking the file up we ensure that compilation won't
break.

Corresponding to flashrom svn r1208.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      b30a5ed4
  5. 08 Oct, 2010 6 commits
  7. 07 Oct, 2010 1 commit
  9. 06 Oct, 2010 4 commits
  11. 05 Oct, 2010 11 commits
  13. 30 Sep, 2010 1 commit
  15. 29 Sep, 2010 1 commit
  17. 26 Sep, 2010 1 commit
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  21. 20 Sep, 2010 1 commit
  23. 18 Sep, 2010 1 commit
  25. 16 Sep, 2010 3 commits
  27. 15 Sep, 2010 5 commits
    • Mattias Mattsson's avatar
      This patch changes the prefix of chip constant #defines in the following way · 6eabe282
      Mattias Mattsson authored 
      AM_* -> AMD_AM*
AT_* -> ATMEL_AT*
EN_* -> EON_EN*
HY_* -> HYUNDAI_HY*
MBM* -> FUJITSU_MBM*
MX_ID -> MACRONIX_ID
MX_* -> MACRONIX_MX*
PMC_* -> PMC_PM*
SST_* -> SST_SST*

It leaves the Intel #defines alone because there is another pending
patch for that:
http://patchwork.coreboot.org/patch/1937/

Some background discussion here:
http://www.flashrom.org/pipermail/flashrom/2010-July/004059.html



Corresponding to flashrom svn r1175.
Signed-off-by: default avatarMattias Mattsson <vitplister@gmail.com>
Acked-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
      6eabe282
    • Joshua Roys's avatar
      Add chipset enable for Broadcom OSB4 · 85835d89
      Joshua Roys authored 
      
No docs available.

Corresponding to flashrom svn r1174.
Signed-off-by: default avatarJoshua Roys <roysjosh@gmail.com>
Acked-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
      85835d89
    • Carl-Daniel Hailfinger's avatar
      Detect embedded EC (IMC) in AMD's SBs · 39446e34
      Carl-Daniel Hailfinger authored 
      
AMD SB700 and later have an integrated microcontroller (IMC) which runs
from shared flash.

The IMC will happily issue reads while we write, issue writes while we
read, and generally cause lots of havoc due to the concurrent accesses
it performs while flashrom is running. A failing or corrupted read can
be detected since r1145, and the worst case is that the read aborts and
the user has to retry. A failing write is much more serious. It can
be detected since r1145, but if the SPI interface locks up, we can't
continue writing nor can we read the current chip contents.

If the IMC is inactive, there is no reason to worry. If the IMC is
active, flashrom will refuse to erase/write the chip with this patch.

The correct fix would be to stop the IMC during flashing, but apparently
the relevant registers are undocumented, so we take the safe route for
now until someone from AMD can give us more info.

Corresponding to flashrom svn r1173.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: default avatarMatthias Kretz <kretz@kde.org>
Acked-by: default avatarUwe Hermann <uwe@hermann-uwe.de>
      39446e34
    • Carl-Daniel Hailfinger's avatar
      Delay between probe and subsequent operations · 9ad4255b
      Carl-Daniel Hailfinger authored 
      
Some flash chips need time to exit ID mode, and while we take care of
correct timing for the matching probe, subsequent probes may have
totally different timing, and that can lead to garbage responses from
the flash chip during the first accesses after the probe sequence is
done.
Delay 100 ms between the last probe and any subsequent operation.
To ensure maximum correctness, we would have to reset the chip first in
case the last probe function left the chip in an undefined (non-read)
state. That will be possible once struct flashchip has a .reset
function.

This fixes unstable erase/read/write for some flahs chips on nic3com and
possible other use cases as well.

Thanks to Maciej Pijanka for reporting the issue and testing patches.

Corresponding to flashrom svn r1172.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarMichael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
      9ad4255b
    • Carl-Daniel Hailfinger's avatar
      SPI bitbanging: request/release bus · 2822888c
      Carl-Daniel Hailfinger authored 
      SPI bitbanging on devices which speak SPI natively has a dual-use
problem: We need to shut down normal SPI operations to do the bitbanging
ourselves. Once we're done, it makes a lot of sense to reenable "normal"
SPI operations again. Add request_bus/release_bus functions to struct
bitbang_spi_master.
Add a bitbang shutdown function (not used yet).
Change MCP SPI and Intel NIC SPI to use the new request/release bus
infrastructure.
Cosmetic changes to a few error messages (80 column limit).

There are multiple possible strategies for bus request/release:
- Request at the start of a SPI command, release immediately afterwards.
- Request at the start of a SPI multicommand, release once all commands
of the multicommand are done.
- Request on programmer init, release on shutdown.
Each strategy has its own advantages. For now, we will stay with the
first strategy which worked fine so far.

Corresponding to flashrom svn r1171.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfin...
      2822888c

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