GitLab

Among others, I have seen the following problems: - The SPI opcode is
not supported by the controller. ICH-style controllers exhibit this if
SPI config is locked down. - The address in in a prohibited area. This
can happen on ICH for any access (BBAR) and for writes in chipset write
protected areas. - There is no SPI controller.

Introduce separate error codes for unsupported opcode and prohibited
address.

Add the ability to adjust REMS and RES addresses to the minium supported
read address with the help of spi_get_valid_read_addr(). That function
needs to call SPI controller specific functions like reading BBAR on
ICH.

Corresponding to flashrom svn r500.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

This allows flashrom to identify, read, write, erase and verify flash chips
on (some) 3COM network cards. The patch uses the external programmer
infrastructure, the network card is basically treated as an external
flash programmer.

Usage:

$ ./flashrom -p nic3com
flashrom v0.9.0-r498
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200), addr = 0xa400
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
No operations were specified.

$ ./flashrom -p nic3com -E
flashrom v0.9.0-r498
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200), addr = 0xa400
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
Erasing flash chip... SUCCESS.

$ ./flashrom -p nic3com -wv backup.bin
flashrom v0.9.0-r498
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200), addr = 0xa400
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
Flash image seems to be a legacy BIOS. Disabling checks.
Programming page: 1023 at address: 0x0000ffc0
Verifying flash... VERIFIED.

$ ./flashrom -p nic3com -r backup.bin
flashrom v0.9.0-r498
Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200), addr = 0xa400
Calibrating delay loop... OK.
Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000.
Reading flash... done.

I have tested this on actual hardware (see PCI IDs above) and all
operations worked fine.

Support for other 3COM cards will follow (I added some more which should
be supportable by this code, but they're untested so far), as well as
support for NICs from other vendors.

The patch also adds support for the Atmel AT49BV512 which is soldered
onto the 3COM NIC I used for testing.

Corresponding to flashrom svn r499.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Flash mapping/unmapping was performed without an abstraction layer,
so even the dummy flasher caused memory mappings to be set up. Add
map/unmap functions to the external flasher abstraction.

Fix a possible scribble-over-low-memory corner case which fortunately
never triggered so far.

With this patch, --programmer dummy works fine as non-root.

Corresponding to flashrom svn r493.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Change the flashchips entry for SST SST25VF080B to 1-byte writing.

Tested-by: Ali Nadalizadeh.

Corresponding to flashrom svn r486.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Change SPI architecture to handle 1-byte chunk chip writing differently
from 256-byte chunk chip writing.

Annotate SPI chip write functions with _256 or _1 suffix denoting the
number of bytes they write at maximum.

The 1-byte chunk writing is cut-n-pasted to different SPI drivers right
now. A later patch can move them to the generic spi_chip_write_1.

Corresponding to flashrom svn r485.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Usage:
flashrom --programmer dummy

This is a great way to test flashrom without root access.

Corresponding to flashrom svn r483.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

- Read/write accesses through function pointers
- Command line parameter for internal/external flasher
- Board and chipset setup moved to internal init function
- Shutdown stuff moved to internal shutdown function

As a side benefit, this will allow us to undo chipset write enable
during shutdown.

Tested by Uwe on real hardware.

Corresponding to flashrom svn r476.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Flashrom assumes that the flash chip contents are available via mmap if
no read function is defined.

This special case is handled in lots of places all over the code.

Remove the special case and use the read_memmapped function. Not only
does this allow us to fix a read bug in flashrom I recently uncovered on
ICH SPI, it also allows us to add support for Paraflasher to flashrom.

Corresponding to flashrom svn r473.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

ASD chips may exist, but all available docs suggest they are just
rebranded Winbond chips with Winbond IDs. The ASD vendor/chip IDs in
flash.h are very likely just misinterpreted LHA headers.

Corresponding to flashrom svn r470.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Fix compilation on Solaris and tell people how to compile flashrom on
Solaris, Darwin/Mac OS X and DragonFly BSD.

Thanks to Joerg Schilling and Patrick Georgi for the Solaris part.

Corresponding to flashrom svn r452.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

Make that explicit in the associated prototypes. This avoids a warning
on some compilers and is a correctness issue.

Corresponding to flashrom svn r449.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

There are still some tweaks necessary to get flashrom to build on
DragonFly, but this helps a lot.

Corresponding to flashrom svn r445.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Also, fix smaller cosmetics

Corresponding to flashrom svn r442 and coreboot v2 svn r4205.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r441 and coreboot v2 svn r4200.
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r437 and coreboot v2 svn r4150.
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Acked-by: Peter Stuge <peter@stuge.se>

Before we attempt trickery, we can simply rename the accessor functions.

Patch created with the help of Coccinelle.

Corresponding to flashrom svn r420 and coreboot v2 svn r3984.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>

Right now we perform direct pointer manipulation without any abstraction
to read from and write to memory mapped flash chips. That makes it
impossible to drive any flasher which does not mmap the whole chip.

Using helper functions readb() and writeb() allows a driver for external
flash programmers like Paraflasher to replace readb and writeb with
calls to its own chip access routines.

This patch has the additional advantage of removing lots of unnecessary
casts to volatile uint8_t * and now-superfluous parentheses which caused
poor readability.

I used the semantic patcher Coccinelle to create this patch. The
semantic patch follows:
@@
expression a;
typedef uint8_t;
volatile uint8_t *b;
@@
- *(b) = (a);
+ writeb(a, b);
@@
volatile uint8_t *b;
@@
- *(b)
+ readb(b)
@@
type T;
T b;
@@
(
 readb
|
 writeb
)
 (...,
- (T)
- (b)
+ b
 )

In contrast to a sed script, the semantic patch performs type checking
before converting anything.

Tested-by: Joe Julian

Corresponding to flashrom svn r418 and coreboot v2 svn r3971.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>

T/NT TEST_OK_ PROBE READ ERASE WRITE

Test report from Julia. Thanks!

Corresponding to flashrom svn r409 and coreboot v2 svn r3917.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Julia Longtin <juri@solarnetone.org>

SST AAI is Auto Address Increment writing, a streamed write to the flash chip
where the first write command sets a starting address and following commands
simply append data. Unfortunately not supported by Winbond SPI masters.

From July 2008.

Corresponding to flashrom svn r407 and coreboot v2 svn r3913.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!

Corresponding to flashrom svn r404 and coreboot v2 svn r3910.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>

Corresponding to flashrom svn r403 and coreboot v2 svn r3909.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Through DirectIO from coresystems GmbH we now support Darwin/Mac OS X.
DirectIO is available at http://www.coresystems.de/en/directio



Corresponding to flashrom svn r399 and coreboot v2 svn r3905.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r397 and coreboot v2 svn r3903.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

The function exit()s on failure, and no callers check the return value.

Corresponding to flashrom svn r396 and coreboot v2 svn r3901.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r393 and coreboot v2 svn r3898.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r386 and coreboot v2 svn r3890.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>

Corresponding to flashrom svn r373 and coreboot v2 svn r3850.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

* add a generic preop-opcode-pair table.

* rename ich_check_opcodes to ich_init_opcodes.

* let ich_init_opcodes do not need to access flashchip structure:
  . move the definition of struct preop_opcode_pair to a better place
  . remove preop_opcode_pairs from 'struct flashchip'
  . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure

* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.

* fix a coding style mistake.

Corresponding to flashrom svn r367 and coreboot v2 svn r3814.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>

MX29LV040C probe and read support tested by khetzal on IRC.

Corresponding to flashrom svn r366 and coreboot v2 svn r3809.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Corresponding to flashrom svn r364 and coreboot v2 svn r3805.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

SST_25VF512A_REMS
SST_25VF010_REMS
SST_25VF020_REMS
SST_25VF040_REMS
SST_25VF040B_REMS
SST_25VF080_REMS
SST_25VF080B_REMS
SST_25VF032B_REMS
SST_26VF016
SST_26VF032
W_25X16
W_25X32
W_25X64

Straight from the data sheets.

The REMS IDs help in case the RDID opcode is unavailable (due to opcode
lockdown) or unsupported by the chip.

Some day, we need to pair probe functions together with IDs. Multiple
pairs can exist per chip and duplicating chip definitions does not
really make sense.

Corresponding to flashrom svn r358 and coreboot v2 svn r3793.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Fixes #109

Corresponding to flashrom svn r355 and coreboot v2 svn r3790.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

If a chip has any TEST_BAD_* flag set, we don't even list the
unsupported functions, giving the user the impression that the
unsupported functions are tested.

Corresponding to flashrom svn r352 and coreboot v2 svn r3780.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

This has been tested by Uwe Hermann on an RS690/SB600 board.

Corresponding to flashrom svn r351 and coreboot v2 svn r3779.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID

RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.

The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES

Corresponding to flashrom svn r349 and coreboot v2 svn r3775.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

Although SPI itself does not have a mechanism to signal command failure,
the SPI host may be unable to send a given command over the wire due
to security or hardware limitations. The current code ignores these
mechanisms completely and simply assumes almost every command succeeds.
Complain if SPI command execution fails.

Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.

Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.

Corresponding to flashrom svn r345 and coreboot v2 svn r3757.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>

The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.

Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D

Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642

Add the ID, but no probing function for this chip:
AT25F512A

Corresponding to flashrom svn r342 and coreboot v2 svn r3754.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>

Replace age-old TODO comments with real explanations.

Fixed chips:
Fujitsu MBM29F400TC (ID definition)
Macronix MX29F002T (chip name)

New chips:
Fujitsu MBM29F004BC
Fujitsu MBM29F004TC
Fujitsu MBM29F400BC
Macronix MX25L512
Macronix MX25L1005
Macronix MX25L2005
Macronix MX25L6405
Macronix MX29F002B

Straight from the data sheets, compile tested only.

Corresponding to flashrom svn r339 and coreboot v2 svn r3730.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

Not all chips support all commands, so allow the implementer to select
the matching function. Fix a layering violation in ICH SPI code to be
less bad. Still not perfect, but the new code is shorter, more generic
and architecturally more sound.

TODO (in a separate patch): - move the generic sector erase code to
spi.c - decide which erase command to use based on info about the chip -
create a generic spi_erase_all_sectors function which calls the generic
sector erase function

Thanks to Stefan for reviewing and commenting.

Corresponding to flashrom svn r337 and coreboot v2 svn r3722.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Identification only, erase/write are not implemented.

Corresponding to flashrom svn r335 and coreboot v2 svn r3717.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

tested and
Acked-by: Elia Yehuda <z4ziggy@gmail.com>