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  17. 15 Dec, 2008 1 commit
    • FENG yu ning's avatar
      Various ichspi.c refinements · f041e9b5
      FENG yu ning authored 
      
* add a generic preop-opcode-pair table.

* rename ich_check_opcodes to ich_init_opcodes.

* let ich_init_opcodes do not need to access flashchip structure:
  . move the definition of struct preop_opcode_pair to a better place
  . remove preop_opcode_pairs from 'struct flashchip'
  . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure

* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.

* fix a coding style mistake.

Corresponding to flashrom svn r367 and coreboot v2 svn r3814.
Signed-off-by: default avatarFENG yu ning <fengyuning1984@gmail.com>
Acked-by: default avatarPeter Stuge <peter@stuge.se>
      f041e9b5
  19. 10 Dec, 2008 1 commit
  21. 08 Dec, 2008 3 commits
  23. 06 Dec, 2008 1 commit
  25. 05 Dec, 2008 3 commits
  27. 04 Dec, 2008 1 commit
  29. 03 Dec, 2008 3 commits
  31. 29 Nov, 2008 1 commit
  33. 28 Nov, 2008 5 commits
  35. 27 Nov, 2008 1 commit
    • Carl-Daniel Hailfinger's avatar
      Try RES even if RDID fails · 92a54ca0
      Carl-Daniel Hailfinger authored 
      
The existing check in probe_spi_res() was right for SPI controllers
which support all commands, but may not exist. For controllers which
support only a subset of commands, it will fail in unexpected ways. Even
if a command is supported by the controller, it may be unavailable if
the controller is locked down.

The new logic checks if RDID could be issued and its return values
made sense (not 0xff 0xff 0xff). In that case, RES probing is not
performed. Otherwise, we try RES. There is one drawback: If RDID
returned unexpected values, we don't issue a RES probe. However, in that
case we should try to match RDID anyway.

Corresponding to flashrom svn r348 and coreboot v2 svn r3774.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarFENG yu ning <fengyuning1984@gmail.com>
      92a54ca0
  37. 24 Nov, 2008 1 commit
  39. 18 Nov, 2008 2 commits
    • Carl-Daniel Hailfinger's avatar
      ichspi: use spi_nbyte_read() instead of running the opcode directly · 738fdffe
      Carl-Daniel Hailfinger authored 
      
Currently flashrom assumes every vendor BIOS shares our view about which
SPI opcodes should be placed in which location.

Move to a less optimistic implementation and actually use the generic
SPI read functions. They're useful for abstracting exactly this stuff
and that makes them the preferred choice.

Corresponding to flashrom svn r346 and coreboot v2 svn r3758.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: default avatarStefan Reinauer <stepan@coresystems.de>
      738fdffe
    • Carl-Daniel Hailfinger's avatar
      Check for failed SPI command execution · 598ec58e
      Carl-Daniel Hailfinger authored 
      
Although SPI itself does not have a mechanism to signal command failure,
the SPI host may be unable to send a given command over the wire due
to security or hardware limitations. The current code ignores these
mechanisms completely and simply assumes almost every command succeeds.
Complain if SPI command execution fails.

Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.

Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.

Corresponding to flashrom svn r345 and coreboot v2 svn r3757.
Signed-off-by: default avatarCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
      598ec58e

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