- 31 May, 2009 1 commit
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Carl-Daniel Hailfinger authored
Right now, the annotation only differentiates between SPI and non-SPI. Anyone who knows more about a specific flash chip should feel free to update it. The existing flashbus variable was abused to denote the SPI controller type. Use an aptly named variable for that purpose. Once this patch is merged, the chipset/programmer init functions can set supported flash chip types and flashrom can automatically select only matching probe/read/erase/write functions. A side benefit of that will be the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict. Corresponding to flashrom svn r556. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Uwe Hermann <uwe@hermann-uwe.de>
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- 27 May, 2009 1 commit
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Carl-Daniel Hailfinger authored
Every chip besides SPI and w39v080fa uses id1/id2 as local variable names to store ID responses from the flash chip. This eases grepping a lot. As a bonus, it also frees up some names to be used as parameters. Corresponding to flashrom svn r551. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Patrick Georgi <patrick.georgi@coresystems.de>
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- 16 May, 2009 1 commit
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Uwe Hermann authored
Build-tested on 32bit x86. Corresponding to flashrom svn r521. Signed-off-by:
Uwe Hermann <uwe@hermann-uwe.de> Acked-by:
Uwe Hermann <uwe@hermann-uwe.de>
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- 15 May, 2009 1 commit
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Carl-Daniel Hailfinger authored
Until the ICH SPI driver can handle preopcodes as standalone opcodes, we should handle such special opcode failure gracefully on ICH and compatible chipsets. This fixes status register writes on almost all ICH+VIA SPI masters. The fix is almost identical to r484, but this time it affects the EWSR (Enable Write Status Register) opcode instead of the WREN (Write Enable) opcode. With the differentiated return codes introduced in r500, the workaround is more precise this time. The old WREN workaround was updated as well. Corresponding to flashrom svn r514. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
FENG Yu Ning <fengyuning1984@gmail.com> Acked-by:
Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
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- 14 May, 2009 1 commit
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Carl-Daniel Hailfinger authored
Does not support reading or writing the fake chip yet. flashrom --programmer dummy also enables the dummy SPI controller driver. Testing the dummy SPI driver revealed a RDID debug printing bug in the SPI core. Fix that as well. Corresponding to flashrom svn r507. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Uwe Hermann <uwe@hermann-uwe.de>
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- 13 May, 2009 2 commits
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Carl-Daniel Hailfinger authored
Even if we don't tell the user about the areas the block locking bits correspond to, printing a detailed list of which lock bits are set is a definite improvement. Corresponding to flashrom svn r505. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Sample output: [...] Probing for SST SST25VF032B, 4096 KB: RDID returned bf 25 4a. probe_spi_rdid_generic: id1 0xbf, id2 0x254a Chip status register is 1c Chip status register: Block Protect Write Disable (BPL) is not set Chip status register: Auto Address Increment Programming (AAI) is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is set Chip status register: Bit 3 / Block Protect 1 (BP1) is set Chip status register: Bit 2 / Block Protect 0 (BP0) is set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "SST SST25VF032B" (4096 KB) at physical address 0xffc00000. Acked-by:
Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
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Carl-Daniel Hailfinger authored
Among others, I have seen the following problems: - The SPI opcode is not supported by the controller. ICH-style controllers exhibit this if SPI config is locked down. - The address in in a prohibited area. This can happen on ICH for any access (BBAR) and for writes in chipset write protected areas. - There is no SPI controller. Introduce separate error codes for unsupported opcode and prohibited address. Add the ability to adjust REMS and RES addresses to the minium supported read address with the help of spi_get_valid_read_addr(). That function needs to call SPI controller specific functions like reading BBAR on ICH. Corresponding to flashrom svn r500. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Uwe Hermann <uwe@hermann-uwe.de>
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- 09 May, 2009 3 commits
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Carl-Daniel Hailfinger authored
Change the flashchips entry for SST SST25VF080B to 1-byte writing. Tested-by: Ali Nadalizadeh. Corresponding to flashrom svn r486. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Carl-Daniel Hailfinger authored
Change SPI architecture to handle 1-byte chunk chip writing differently from 256-byte chunk chip writing. Annotate SPI chip write functions with _256 or _1 suffix denoting the number of bytes they write at maximum. The 1-byte chunk writing is cut-n-pasted to different SPI drivers right now. A later patch can move them to the generic spi_chip_write_1. Corresponding to flashrom svn r485. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Carl-Daniel Hailfinger authored
Until the ICH SPI driver can handle preopcodes as standalone opcodes, we should handle such special opcode failure gracefully on ICH and compatible chipsets. This fixes chip erase on almost all ICH+VIA SPI masters. Thanks to Ali Nadalizadeh for helping track down this bug! Corresponding to flashrom svn r484. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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- 06 May, 2009 1 commit
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Carl-Daniel Hailfinger authored
- Using a 4-bit index into an array with 8 elements leads to out-of-bounds accesses. Use proper bit masking to fix this. - Factor out common SST25 status register printing. - Use the common SST25 status register printing for SST25VF080B. Corresponding to flashrom svn r468. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se>
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- 15 Apr, 2009 1 commit
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Uwe Hermann authored
Corresponding to flashrom svn r429 and coreboot v2 svn r4117. Signed-off-by:
Uwe Hermann <uwe@hermann-uwe.de> Acked-by:
Uwe Hermann <uwe@hermann-uwe.de>
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- 26 Jan, 2009 3 commits
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Peter Stuge authored
SST AAI is Auto Address Increment writing, a streamed write to the flash chip where the first write command sets a starting address and following commands simply append data. Unfortunately not supported by Winbond SPI masters. From July 2008. Corresponding to flashrom svn r407 and coreboot v2 svn r3913. Signed-off-by:
Peter Stuge <peter@stuge.se> Acked-by:
Peter Stuge <peter@stuge.se>
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Peter Stuge authored
Corresponding to flashrom svn r406 and coreboot v2 svn r3912. Signed-off-by:
Peter Stuge <peter@stuge.se> Acked-by:
Peter Stuge <peter@stuge.se>
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Peter Stuge authored
Developed and tested to work on Intel D201GLY in July 2008. Tested by a helpful person on IRC whose name I've since forgotten. Sorry! Corresponding to flashrom svn r404 and coreboot v2 svn r3910. Signed-off-by:
Peter Stuge <peter@stuge.se> Acked-by:
Ward Vandewege <ward@gnu.org>
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- 25 Jan, 2009 1 commit
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Peter Stuge authored
Corresponding to flashrom svn r390 and coreboot v2 svn r3895. Signed-off-by:
Peter Stuge <peter@stuge.se> Acked-by:
Peter Stuge <peter@stuge.se>
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- 28 Nov, 2008 2 commits
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Jason Wang authored
This has been tested by Uwe Hermann on an RS690/SB600 board. Corresponding to flashrom svn r351 and coreboot v2 svn r3779. Signed-off-by:
Jason Wang <Qingpei.Wang@amd.com> Reviewed-by:
Joe Bao <zheng.bao@amd.com> Acked-by:
Uwe Hermann <uwe@hermann-uwe.de>
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Carl-Daniel Hailfinger authored
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID - probe_spi_res with opcode 0xab, usually 1 byte ID We are missing the following probe function: - probe_spi_rems with opcode 0x90, usually 2 bytes ID RDID provides best specifity (manufacturer, device class and device) and RES is supported by quite a few old chips. However, RES only returns one byte and there are multiple flash chips with different sizes on the market and all of them have the same RES ID. REMS is from the same age as RES, but it provides a manufacturer and a device ID. It is therefore on par with the probing for parallel flash chips and specific enough. The order in which chips should be detected is as follows: 1. RDID 2. REMS 3. RES Corresponding to flashrom svn r349 and coreboot v2 svn r3775. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se>
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- 27 Nov, 2008 1 commit
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Carl-Daniel Hailfinger authored
The existing check in probe_spi_res() was right for SPI controllers which support all commands, but may not exist. For controllers which support only a subset of commands, it will fail in unexpected ways. Even if a command is supported by the controller, it may be unavailable if the controller is locked down. The new logic checks if RDID could be issued and its return values made sense (not 0xff 0xff 0xff). In that case, RES probing is not performed. Otherwise, we try RES. There is one drawback: If RDID returned unexpected values, we don't issue a RES probe. However, in that case we should try to match RDID anyway. Corresponding to flashrom svn r348 and coreboot v2 svn r3774. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
FENG yu ning <fengyuning1984@gmail.com>
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- 18 Nov, 2008 1 commit
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Carl-Daniel Hailfinger authored
Although SPI itself does not have a mechanism to signal command failure, the SPI host may be unable to send a given command over the wire due to security or hardware limitations. The current code ignores these mechanisms completely and simply assumes almost every command succeeds. Complain if SPI command execution fails. Since locked down Intel chipsets (like the one we had problems with earlier) only allow a small subset of commands, find the common subset of commands between the chipset and the ROM in the chip erase case. That is accomplished by the new spi_chip_erase_60_c7() which can be used for chips supporting both 0x60 and 0xc7 chip erase commands. Both parts of the patch address problems seen in the real world. The increased verbosity for the error case will help us diagnose and address problems better. Corresponding to flashrom svn r345 and coreboot v2 svn r3757. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
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- 03 Nov, 2008 1 commit
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Carl-Daniel Hailfinger authored
Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Corresponding to flashrom svn r337 and coreboot v2 svn r3722. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Stefan Reinauer <stepan@coresystems.de>
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- 29 Oct, 2008 1 commit
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Stefan Reinauer authored
Using block erase d8 as discussed with Peter Stuge Corresponding to flashrom svn r333 and coreboot v2 svn r3707. Signed-off-by:
Stefan Reinauer <stepan@coresystems.de> Acked-by:
Stefan Reinauer <stepan@coresystems.de>
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- 18 Oct, 2008 1 commit
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Uwe Hermann authored
Corresponding to flashrom svn r326 and coreboot v2 svn r3669. Signed-off-by:
Uwe Hermann <uwe@hermann-uwe.de> Acked-by:
Uwe Hermann <uwe@hermann-uwe.de>
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- 07 Jul, 2008 1 commit
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Peter Stuge authored
While writing a new SPI driver I fixed some things in the SPI code: All calls to spi_command() had unneccessary #define duplications, and in some cases the read count define could theoretically become harmful because NULL was passed for the read buffer. Avoid a crash, should someone change the #defines. I also noticed that the only caller of spi_page_program() was the it87 driver, and spi_page_program() could only call back into the it87 driver. Removed the function for easier-to-follow code and made it8716f_spi_page_program() static. The ichspi driver's static page functions are already static. Corresponding to flashrom svn r302 and coreboot v2 svn r3418. Signed-off-by:
Peter Stuge <peter@stuge.se> Acked-by:
Peter Stuge <peter@stuge.se>
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- 30 Jun, 2008 3 commits
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Stefan Reinauer authored
At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Corresponding to flashrom svn r285 and coreboot v2 svn r3401. Signed-off-by:
Stefan Reinauer <stepan@coresystems.de> Acked-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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Rudolf Marek authored
Following patch adds support for that. Corresponding to flashrom svn r283 and coreboot v2 svn r3399. Signed-off-by:
Rudolf Marek <r.marek@assembler.cz> Acked-by:
Peter Stuge <peter@stuge.se>
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Rudolf Marek authored
It is similar with few documented exceptions to ICH7 SPI controller. Corresponding to flashrom svn r282 and coreboot v2 svn r3398. Signed-off-by:
Rudolf Marek <r.marek@assembler.cz> Acked-by:
Peter Stuge <peter@stuge.se>
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- 27 Jun, 2008 1 commit
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Stefan Reinauer authored
* ICH7 SPI support * fix some variable names in ichspi.c (Offset -> offset) * Dump ICH7 SPI bar with -V * Improve error message in case IOPL goes wrong. (It might not even be an IOPL) Corresponding to flashrom svn r278 and coreboot v2 svn r3393. Signed-off-by:
Stefan Reinauer <stepan@coresystems.de> Acked-by:
Peter Stuge <peter@stuge.se>
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- 24 Jun, 2008 1 commit
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Peter Stuge authored
Preparation for a probe optimization patch. This patch does not change any functionality. spi_probe_rdid was tested to still work on my M57SLI rev 2. The idea is to have error checks return error immediately when something fails, rather than having code inside an if block where the condition tests for success. This means: Less indentation, more clear what the code is checking. Corresponding to flashrom svn r272 and coreboot v2 svn r3386. Signed-off-by:
Peter Stuge <peter@stuge.se> Acked-by:
Ward Vandewege <ward@gnu.org>
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- 16 May, 2008 1 commit
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Dominik Geyer authored
This is done by using the generic SPI interface. Corresponding to flashrom svn r239 and coreboot v2 svn r3325. Signed-off-by:
Dominik Geyer <dominik.geyer@kontron.com> Acked-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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- 15 May, 2008 2 commits
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Carl-Daniel Hailfinger authored
Corresponding to flashrom svn r237 and coreboot v2 svn r3323. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se>
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Carl-Daniel Hailfinger authored
Add support for the JEDEC RES (Read Electronic Signature and Resume from Powerdown) SPI command to identify older SPI chips which can't handle JEDEC RDID. Since RES gives a one-byte identifier which is shared among many different vendors and even different sizes, we want to match RES as a last resort if RDID returns 0xff 0xff 0xff. Corresponding to flashrom svn r235 and coreboot v2 svn r3320. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se> This is a heavily reworked version of a patch by Fredrik Tolf, which was Signed-off-by:
Fredrik Tolf <fredrik@dolda2000.com>
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- 14 May, 2008 1 commit
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Carl-Daniel Hailfinger authored
Flash chips which can be detected by JEDEC probe routines all have vendor IDs with correct parity. Use a parity check as additional hint whether a vendor ID makes sense. Note: Device IDs have no parity requirements whatsoever. Corresponding to flashrom svn r231 and coreboot v2 svn r3308. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se>
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- 13 May, 2008 3 commits
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Carl-Daniel Hailfinger authored
No behavioural changes, but greatly improved SPI abstraction. Corresponding to flashrom svn r229 and coreboot v2 svn r3305. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se>
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Carl-Daniel Hailfinger authored
This patch has no code changes. Corresponding to flashrom svn r228 and coreboot v2 svn r3302. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se>
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Carl-Daniel Hailfinger authored
In theory, this patch has no behaviour changes. Corresponding to flashrom svn r227 and coreboot v2 svn r3301. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se>
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- 10 May, 2008 2 commits
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Carl-Daniel Hailfinger authored
This paves the way to have a fully generic generic_spi_command without knowledge about any SPI controller. The third step would be calling SPI controller functions via a function pointer. Corresponding to flashrom svn r224 and coreboot v2 svn r3296. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Peter Stuge <peter@stuge.se>
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Peter Stuge authored
This is a very early step toward cleaning up SPI code in flashrom. Corresponding to flashrom svn r223 and coreboot v2 svn r3295. Signed-off-by:
Peter Stuge <peter@stuge.se> Acked-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
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- 06 Feb, 2008 1 commit
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Carl-Daniel Hailfinger authored
Some vendors like Programmable Micro Corp (PMC) need this. Both the serial and parallel flash JEDEC detection routines would benefit from a parity/sanity check of the vendor ID. Will do this later. Add support for the PMC Pm25LV family of SPI flash chips. Corresponding to flashrom svn r191 and coreboot v2 svn r3091. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Chris Lingard <chris@stockwith.co.uk>
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- 22 Jan, 2008 1 commit
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Carl-Daniel Hailfinger authored
Minor formatting changes. Corresponding to flashrom svn r184 and coreboot v2 svn r3069. Signed-off-by:
Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by:
Harald Gutmann <harald.gutmann@gmx.net>
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