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Commit bf4e83d5 authored by Raptor Engineering Development Team's avatar Raptor Engineering Development Team
Browse files

Add option to use USRMCLK on ECP5 instead of a direct clock pin

parent b1bdcdd5
......@@ -25,7 +25,7 @@ mB = 1024*kB
# SPI interface ------------------------------------------------------------------------------------
class TercelSPI(Module, AutoCSR):
def __init__(self, platform, pads, clk_freq, endianness="big", adr_offset=0x0, debug_signals=None):
def __init__(self, platform, pads, clk_freq, endianness="big", adr_offset=0x0, lattice_ecp5_usrmclk=False, debug_signals=None):
self.bus = bus = wishbone.Interface(data_width=32, adr_width=30)
self.cfg_bus = cfg_bus = wishbone.Interface(data_width=32, adr_width=30)
self.cs_n = cs_n = Signal()
......@@ -142,7 +142,13 @@ class TercelSPI(Module, AutoCSR):
i = self.spi_d3_in,
)
self.comb += pads.cs_n.eq(self.spi_ss_n)
self.comb += pads.clk.eq(self.spi_clock)
if lattice_ecp5_usrmclk:
self.specials += Instance("USRMCLK",
i_USRMCLKI = self.spi_clock,
i_USRMCLKTS = 0
)
else:
self.comb += pads.clk.eq(self.spi_clock)
if debug_signals is not None:
self.comb += debug_signals[0].eq(self.spi_d0_in)
......
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