Commit b1bdcdd5 authored by Raptor Engineering Development Team's avatar Raptor Engineering Development Team
Browse files

Break up Wishbone master and SPI PHY files

parent 775cae78
......@@ -158,4 +158,5 @@ class TercelSPI(Module, AutoCSR):
@staticmethod
def add_sources(platform):
vdir = get_data_mod("peripheral", "tercelspi").data_location
platform.add_source(os.path.join(vdir, "spi_master.v"))
\ No newline at end of file
platform.add_source(os.path.join(vdir, "wishbone_spi_master.v"))
platform.add_source(os.path.join(vdir, "phy.v"))
\ No newline at end of file
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