Unverified Commit 6bb3837b authored by Paul Mackerras's avatar Paul Mackerras Committed by GitHub
Browse files

Merge pull request #194 from ozbenh/misc

Fix syscon registers usage and add "save" function to mw_debug
parents 13da4caa 183d05de
......@@ -8,3 +8,5 @@ tests/*/*.bin
tests/*/*.hex
tests/*/*.elf
TAGS
litedram/build/*
obj_dir/*
......@@ -91,9 +91,6 @@ begin
wb_ctrl_is_csr => wb_dram_is_csr,
wb_ctrl_is_init => wb_dram_is_init,
serial_tx => open,
serial_rx => '1',
init_done => open,
init_error => open,
......
......@@ -61,9 +61,6 @@ begin
wb_ctrl_is_csr => '0',
wb_ctrl_is_init => '0',
serial_tx => open,
serial_rx => '1',
init_done => open,
init_error => open,
......
......@@ -26,12 +26,6 @@ entity toplevel is
uart_main_tx : out std_ulogic;
uart_main_rx : in std_ulogic;
-- DRAM UART signals (PMOD)
uart_pmod_tx : out std_ulogic;
uart_pmod_rx : in std_ulogic;
uart_pmod_cts_n : in std_ulogic;
uart_pmod_rts_n : out std_ulogic;
-- LEDs
led0_b : out std_ulogic;
led0_g : out std_ulogic;
......@@ -110,8 +104,6 @@ architecture behaviour of toplevel is
constant PAYLOAD_SIZE : natural := get_payload_size;
begin
uart_pmod_rts_n <= '0';
-- Main SoC
soc0: entity work.soc
generic map(
......@@ -232,9 +224,6 @@ begin
wb_ctrl_is_csr => wb_dram_is_csr,
wb_ctrl_is_init => wb_dram_is_init,
serial_tx => uart_pmod_tx,
serial_rx => uart_pmod_rx,
init_done => dram_init_done,
init_error => dram_init_error,
......
......@@ -212,9 +212,6 @@ begin
wb_ctrl_is_csr => wb_dram_is_csr,
wb_ctrl_is_init => wb_dram_is_init,
serial_tx => open,
serial_rx => '0',
init_done => dram_init_done,
init_error => dram_init_error,
......
......@@ -25,8 +25,11 @@
#define SYS_REG_INFO_HAS_DRAM (1ull << 1)
#define SYS_REG_INFO_HAS_BRAM (1ull << 2)
#define SYS_REG_BRAMINFO 0x10
#define SYS_REG_BRAMINFO_SIZE_MASK 0xfffffffffffffull
#define SYS_REG_DRAMINFO 0x18
#define SYS_REG_DRAMINFO_SIZE_MASK 0xfffffffffffffull
#define SYS_REG_CLKINFO 0x20
#define SYS_REG_CLKINFO_FREQ_MASK 0xffffffffffull
#define SYS_REG_CTRL 0x28
#define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0)
#define SYS_REG_CTRL_CORE_RESET (1ull << 1)
......
......@@ -75,7 +75,7 @@ void potato_uart_init(void)
uint64_t proc_freq;
potato_uart_base = UART_BASE;
proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO);
proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(proc_freq, UART_FREQ));
}
......
......@@ -52,10 +52,6 @@ entity litedram_wrapper is
wb_ctrl_is_csr : in std_ulogic;
wb_ctrl_is_init : in std_ulogic;
-- Init core serial debug
serial_tx : out std_ulogic;
serial_rx : in std_ulogic;
-- Misc
init_done : out std_ulogic;
init_error : out std_ulogic;
......
......@@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
constant INIT_RAM_SIZE : integer := 16384;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE);
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram_core.init";
type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
......
......@@ -58,16 +58,16 @@ void main(void)
printf("BRAM ");
printf("\n");
if (ftr & SYS_REG_INFO_HAS_BRAM) {
val = readq(SYSCON_BASE + SYS_REG_BRAMINFO);
val = readq(SYSCON_BASE + SYS_REG_BRAMINFO) & SYS_REG_BRAMINFO_SIZE_MASK;
printf(" BRAM: %lld KB\n", val / 1024);
}
if (ftr & SYS_REG_INFO_HAS_DRAM) {
val = readq(SYSCON_BASE + SYS_REG_DRAMINFO);
val = readq(SYSCON_BASE + SYS_REG_DRAMINFO) & SYS_REG_DRAMINFO_SIZE_MASK;
printf(" DRAM: %lld MB\n", val / (1024 * 1024));
val = readq(SYSCON_BASE + SYS_REG_DRAMINITINFO);
printf(" DRAM INIT: %lld KB\n", val / 1024);
}
val = readq(SYSCON_BASE + SYS_REG_CLKINFO);
val = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
printf(" CLK: %lld MHz\n", val / 1000000);
printf("\n");
......
......@@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
constant INIT_RAM_SIZE : integer := 16384;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE);
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram_core.init";
type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
......
......@@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
constant INIT_RAM_SIZE : integer := 16384;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE);
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram_core.init";
type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
......
......@@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
constant INIT_RAM_SIZE : integer := 16384;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE);
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init";
type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
......
......@@ -175,7 +175,11 @@ static int sim_command(uint8_t op, uint8_t addr, uint64_t *data)
printf("%02x ", buf[i]);
printf("\n");
}
write(sim_fd, buf, p - buf);
r = write(sim_fd, buf, p - buf);
if (r < 0) {
fprintf(stderr, "failed to write sim command\n");
return -1;
}
r = read(sim_fd, buf, sizeof(buf));
if (0 && r > 0) {
int i;
......@@ -506,6 +510,37 @@ static void load(const char *filename, uint64_t addr)
if (!(count % 1024))
printf("%x...\n", count);
}
close(fd);
printf("%x done.\n", count);
}
static void save(const char *filename, uint64_t addr, uint64_t size)
{
uint64_t data;
int fd, rc, count;
fd = open(filename, O_WRONLY | O_CREAT, 00666);
if (fd < 0) {
fprintf(stderr, "Failed to open '%s': %s\n", filename, strerror(errno));
exit(1);
}
check(dmi_write(DBG_WB_CTRL, 0x7ff), "writing WB_CTRL");
check(dmi_write(DBG_WB_ADDR, addr), "writing WB_ADDR");
count = 0;
for (;;) {
check(dmi_read(DBG_WB_DATA, &data), "reading WB_DATA");
rc = write(fd, &data, 8);
if (rc <= 0) {
fprintf(stderr, "Failed to write: %s\n", strerror(errno));
break;
}
count += 8;
if (!(count % 1024))
printf("%x...\n", count);
if (count >= size)
break;
}
close(fd);
printf("%x done.\n", count);
}
......@@ -523,9 +558,10 @@ static void usage(const char *cmd)
fprintf(stderr, "\n");
fprintf(stderr, " Memory:\n");
fprintf(stderr, " mr <hex addr>\n");
fprintf(stderr, " mr <hex addr> [count]\n");
fprintf(stderr, " mw <hex addr> <hex value>\n");
fprintf(stderr, " load <file> [addr] If omitted address is 0\n");
fprintf(stderr, " save <file> <addr> <size>\n");
fprintf(stderr, "\n");
fprintf(stderr, " Registers:\n");
......@@ -651,6 +687,16 @@ int main(int argc, char *argv[])
if (((i+1) < argc) && isdigit(argv[i+1][0]))
addr = strtoul(argv[++i], NULL, 16);
load(filename, addr);
} else if (strcmp(argv[i], "save") == 0) {
const char *filename;
uint64_t addr, size;
if ((i+3) >= argc)
usage(argv[0]);
filename = argv[++i];
addr = strtoul(argv[++i], NULL, 16);
size = strtoul(argv[++i], NULL, 16);
save(filename, addr, size);
} else if (strcmp(argv[i], "gpr") == 0) {
uint64_t reg, count = 1;
......
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