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Kestrel Collaboration
Kestrel LiteX
migen
Commits
5dc0b236
Commit
5dc0b236
authored
5 years ago
by
Sebastien Bourdeauducq
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sayma_rtm: select correct speed grade and IDCODE for v2
parent
98a075c3
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migen/build/platforms/sinara/sayma_rtm2.py
migen/build/platforms/sinara/sayma_rtm2.py
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migen/build/platforms/sinara/sayma_rtm2.py
View file @
5dc0b236
...
@@ -108,7 +108,7 @@ class Platform(XilinxPlatform):
...
@@ -108,7 +108,7 @@ class Platform(XilinxPlatform):
default_clk_period
=
20.0
default_clk_period
=
20.0
def
__init__
(
self
,
larger
=
False
):
def
__init__
(
self
,
larger
=
False
):
chip
=
"xc7a50t-csg325-
1
"
if
larger
else
"xc7a
1
5t-csg325-
1
"
chip
=
"xc7a50t-csg325-
3
"
if
larger
else
"xc7a
3
5t-csg325-
3
"
XilinxPlatform
.
__init__
(
self
,
chip
,
_io
,
XilinxPlatform
.
__init__
(
self
,
chip
,
_io
,
toolchain
=
"vivado"
,
name
=
"sayma_rtm"
)
toolchain
=
"vivado"
,
name
=
"sayma_rtm"
)
self
.
toolchain
.
bitstream_commands
.
extend
([
self
.
toolchain
.
bitstream_commands
.
extend
([
...
...
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