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Kestrel Collaboration
Kestrel LiteX
migen
Commits
98a075c3
Commit
98a075c3
authored
5 years ago
by
Sebastien Bourdeauducq
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sayma_rtm: update for v2.0rc4
parent
cd71a2a7
Changes
1
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1 changed file
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53 additions
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42 deletions
+53
-42
migen/build/platforms/sinara/sayma_rtm2.py
migen/build/platforms/sinara/sayma_rtm2.py
+53
-42
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migen/build/platforms/sinara/sayma_rtm2.py
View file @
98a075c3
...
...
@@ -3,74 +3,85 @@ from migen.build.xilinx import XilinxPlatform
_io
=
[
(
"clk50"
,
0
,
Pins
(
"
R2
"
),
IOStandard
(
"LVCMOS25"
)),
(
"clk50"
,
0
,
Pins
(
"
T14
"
),
IOStandard
(
"LVCMOS25"
)),
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"
C16
"
)),
Subsignal
(
"rx"
,
Pins
(
"
B
17"
)),
Subsignal
(
"tx"
,
Pins
(
"
T17
"
)),
Subsignal
(
"rx"
,
Pins
(
"
U
17"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"amc_rtm_serwb"
,
0
,
Subsignal
(
"clk_p"
,
Pins
(
"P
1
4"
),
Misc
(
"DIFF_TERM=TRUE"
)),
# LVDS26_CC_P
Subsignal
(
"clk_n"
,
Pins
(
"
R15
"
),
Misc
(
"DIFF_TERM=TRUE"
)),
# LVDS26_CC_N
Subsignal
(
"tx_p"
,
Pins
(
"
T17
"
)),
# LVDS27_P
Subsignal
(
"tx_n"
,
Pins
(
"
U17
"
)),
# LVDS27_N
Subsignal
(
"rx_p"
,
Pins
(
"
R18
"
),
Misc
(
"DIFF_TERM=TRUE"
)),
# LVDS25_P
Subsignal
(
"rx_n"
,
Pins
(
"
T18
"
),
Misc
(
"DIFF_TERM=TRUE"
)),
# LVDS25_N
Subsignal
(
"clk_p"
,
Pins
(
"P4"
),
Misc
(
"DIFF_TERM=TRUE"
)),
# LVDS26_CC_P
Subsignal
(
"clk_n"
,
Pins
(
"
P3
"
),
Misc
(
"DIFF_TERM=TRUE"
)),
# LVDS26_CC_N
Subsignal
(
"tx_p"
,
Pins
(
"
V3
"
)),
# LVDS27_P
Subsignal
(
"tx_n"
,
Pins
(
"
V2
"
)),
# LVDS27_N
Subsignal
(
"rx_p"
,
Pins
(
"
U2
"
),
Misc
(
"DIFF_TERM=TRUE"
)),
# LVDS25_P
Subsignal
(
"rx_n"
,
Pins
(
"
U1
"
),
Misc
(
"DIFF_TERM=TRUE"
)),
# LVDS25_N
IOStandard
(
"LVDS_25"
)
),
# HMC clocking chips (830 and 7043)
(
"hmc_spi"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"
A17
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"clk"
,
Pins
(
"
T18
"
),
Misc
(
"PULLDOWN=TRUE"
)),
# cs[0]=830 cs[1]=7043
# Watch out for the HMC830 SPI mode peculiarity. PULLDOWN CS here
# so that toggling the SPI core offline will make edges.
#TODO
Subsignal("cs_n", Pins("
C8 D16
"), Misc("PULLDOWN=TRUE")),
Subsignal
(
"mosi"
,
Pins
(
"
B16
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"miso"
,
Pins
(
"
D9
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"cs_n"
,
Pins
(
"
K16 R17
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"mosi"
,
Pins
(
"
R18
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"miso"
,
Pins
(
"
J15
"
),
Misc
(
"PULLDOWN=TRUE"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"hmc7043_reset"
,
0
,
Pins
(
"E17"
),
IOStandard
(
"LVCMOS33"
)),
(
"hmc7043_gpo"
,
0
,
Pins
(
"D8"
),
IOStandard
(
"LVCMOS33"
)),
(
"hmc7043_reset"
,
0
,
Pins
(
"J18"
),
IOStandard
(
"LVCMOS33"
)),
(
"hmc7043_gpo"
,
0
,
Pins
(
"L14"
),
IOStandard
(
"LVCMOS33"
)),
(
"rtm_fpga_sysref"
,
0
,
Subsignal
(
"p"
,
Pins
(
"R3"
)),
Subsignal
(
"n"
,
Pins
(
"T2"
)),
IOStandard
(
"LVDS_25"
),
Misc
(
"DIFF_TERM=TRUE"
)
),
(
"rtm_fpga_sysref"
,
1
,
Subsignal
(
"p"
,
Pins
(
"R5"
)),
Subsignal
(
"n"
,
Pins
(
"T5"
)),
IOStandard
(
"LVDS_25"
),
Misc
(
"DIFF_TERM=TRUE"
)
),
# clock mux
(
"clk_src_ext_sel"
,
0
,
Pins
(
"
D1
6"
),
IOStandard
(
"LVCMOS
33
"
)),
(
"clk_src_ext_sel"
,
0
,
Pins
(
"
R
6"
),
IOStandard
(
"LVCMOS
25
"
)),
# DACs
(
"ad9154_spi"
,
0
,
Subsignal
(
"clk"
,
Pins
(
"V
17
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"cs_n"
,
Pins
(
"
V16
"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"mosi"
,
Pins
(
"
R13
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"miso"
,
Pins
(
"
T13
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"clk"
,
Pins
(
"V
4
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"cs_n"
,
Pins
(
"
U4
"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"mosi"
,
Pins
(
"
P6
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"miso"
,
Pins
(
"
P5
"
),
Misc
(
"PULLDOWN=TRUE"
)),
IOStandard
(
"LVCMOS25"
)
),
(
"ad9154_txen"
,
0
,
Pins
(
"U
14 V14
"
),
IOStandard
(
"LVCMOS25"
)),
(
"ad9154_rst_n"
,
0
,
Pins
(
"
U16
"
),
IOStandard
(
"LVCMOS25"
)),
(
"ad9154_txen"
,
0
,
Pins
(
"U
6 U5
"
),
IOStandard
(
"LVCMOS25"
)),
(
"ad9154_rst_n"
,
0
,
Pins
(
"
T3
"
),
IOStandard
(
"LVCMOS25"
)),
(
"ad9154_spi"
,
1
,
Subsignal
(
"clk"
,
Pins
(
"
J16
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"cs_n"
,
Pins
(
"J
15
"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"mosi"
,
Pins
(
"K1
8
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"miso"
,
Pins
(
"K
17
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"clk"
,
Pins
(
"
K2
"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"cs_n"
,
Pins
(
"J
4
"
),
Misc
(
"PULLUP=TRUE"
)),
Subsignal
(
"mosi"
,
Pins
(
"K1"
),
Misc
(
"PULLDOWN=TRUE"
)),
Subsignal
(
"miso"
,
Pins
(
"K
3
"
),
Misc
(
"PULLDOWN=TRUE"
)),
IOStandard
(
"LVCMOS25"
)
),
(
"ad9154_txen"
,
1
,
Pins
(
"L
18 J1
4"
),
IOStandard
(
"LVCMOS25"
)),
(
"ad9154_rst_n"
,
1
,
Pins
(
"
K16
"
),
IOStandard
(
"LVCMOS25"
)),
(
"ad9154_txen"
,
1
,
Pins
(
"L
2 L
4"
),
IOStandard
(
"LVCMOS25"
)),
(
"ad9154_rst_n"
,
1
,
Pins
(
"
J5
"
),
IOStandard
(
"LVCMOS25"
)),
(
"i2c"
,
0
,
Subsignal
(
"scl"
,
Pins
(
"
D13
"
)),
Subsignal
(
"sda"
,
Pins
(
"
C13
"
)),
Subsignal
(
"scl"
,
Pins
(
"
P16
"
)),
Subsignal
(
"sda"
,
Pins
(
"
P15
"
)),
IOStandard
(
"LVCMOS33"
)
),
(
"si5324"
,
0
,
Subsignal
(
"rst_n"
,
Pins
(
"C
9
"
),
IOStandard
(
"LVCMOS
33
"
)),
Subsignal
(
"int"
,
Pins
(
"
D15
"
),
IOStandard
(
"LVCMOS
33
"
))
Subsignal
(
"rst_n"
,
Pins
(
"C
14
"
),
IOStandard
(
"LVCMOS
25
"
)),
Subsignal
(
"int"
,
Pins
(
"
V6
"
),
IOStandard
(
"LVCMOS
25
"
))
),
(
"si5324_clkin"
,
0
,
Subsignal
(
"p"
,
Pins
(
"M
16
"
)),
Subsignal
(
"n"
,
Pins
(
"M1
7
"
)),
Subsignal
(
"p"
,
Pins
(
"M
2
"
)),
Subsignal
(
"n"
,
Pins
(
"M1"
)),
IOStandard
(
"LVDS_25"
),
),
# TODO: rename, this will be muxed with the WR PLL
...
...
@@ -79,16 +90,16 @@ _io = [
Subsignal
(
"n"
,
Pins
(
"B5"
))
),
(
"si5324_clkout_fabric"
,
0
,
Subsignal
(
"p"
,
Pins
(
"
T14
"
)),
Subsignal
(
"n"
,
Pins
(
"
T15
"
)),
IOStandard
(
"LVDS_25"
)
Subsignal
(
"p"
,
Pins
(
"
R2
"
)),
Subsignal
(
"n"
,
Pins
(
"
R1
"
)),
IOStandard
(
"LVDS_25"
)
,
Misc
(
"DIFF_TERM=TRUE"
)
),
#
Slave
SATA connector J1
4
# SATA connector J1
3
(
"sata"
,
0
,
Subsignal
(
"txp"
,
Pins
(
"
D
2"
)),
Subsignal
(
"txn"
,
Pins
(
"
D
1"
)),
Subsignal
(
"rxp"
,
Pins
(
"
C
4"
)),
Subsignal
(
"rxn"
,
Pins
(
"
C
3"
))
Subsignal
(
"txp"
,
Pins
(
"
B
2"
)),
Subsignal
(
"txn"
,
Pins
(
"
B
1"
)),
Subsignal
(
"rxp"
,
Pins
(
"
G
4"
)),
Subsignal
(
"rxn"
,
Pins
(
"
G
3"
))
),
]
...
...
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