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Kestrel Collaboration
Kestrel LiteX
migen
Commits
271d7f08
Commit
271d7f08
authored
6 years ago
by
N. Engelhardt
Committed by
Sébastien Bourdeauducq
6 years ago
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update comment for memory fix (#93)
parent
8c01da61
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migen/fhdl/simplify.py
migen/fhdl/simplify.py
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migen/fhdl/simplify.py
View file @
271d7f08
...
@@ -93,7 +93,7 @@ class MemoryToArray(ModuleTransformer):
...
@@ -93,7 +93,7 @@ class MemoryToArray(ModuleTransformer):
f
.
comb
.
append
(
port
.
dat_r
.
eq
(
storage
[
adr_reg
]))
f
.
comb
.
append
(
port
.
dat_r
.
eq
(
storage
[
adr_reg
]))
elif
port
.
mode
==
NO_CHANGE
and
port
.
we
is
not
None
:
elif
port
.
mode
==
NO_CHANGE
and
port
.
we
is
not
None
:
rd_stmt
=
If
(
~
port
.
we
,
port
.
dat_r
.
eq
(
storage
[
port
.
adr
]))
rd_stmt
=
If
(
~
port
.
we
,
port
.
dat_r
.
eq
(
storage
[
port
.
adr
]))
else
:
#
READ_FIRST or port.we is None, simplest case
else
:
#
NO_CHANGE without write capability reduces to READ_FIRST
rd_stmt
=
port
.
dat_r
.
eq
(
storage
[
port
.
adr
])
rd_stmt
=
port
.
dat_r
.
eq
(
storage
[
port
.
adr
])
if
port
.
re
is
None
:
if
port
.
re
is
None
:
sync
.
append
(
rd_stmt
)
sync
.
append
(
rd_stmt
)
...
...
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